TLK111 datasheet(3/110 Pages) TI1

3 / 110 page

TLK111

www.ti.com

SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014

Introduction

.............................................. 1

5.7

IEEE 1588 Precision Timing Protocol Support

..... 37

1.1

Features

............................................. 1

Reset and Power Down Operation

................. 39

1.2

Applications

.......................................... 1

6.1

Hardware Reset

.................................... 39

1.3

Device Overview

..................................... 1

6.2

Software Reset

..................................... 39

Pin Descriptions

......................................... 4

6.3

Power Down/Interrupt

.............................. 39

2.1

Pin Layout

........................................... 4

6.4

Power Save Modes

................................. 40

2.2

Serial Management Interface (SMI)

................. 5

Design Guidelines

..................................... 41

2.3

MAC Data Interface

.................................. 5

7.1

TPI Network Circuit

................................. 41

2.4

10Mbs and 100Mbs PMD Interface

.................. 6

7.2

Clock In (XI) Requirements

......................... 41

2.5

Clock Interface

....................................... 6

7.3

Thermal Vias Recommendation

.................... 43

2.6

LED Interface

........................................ 6

7.4

Fiber Networking Circuit

............................ 43

2.7

JTAG Interface

....................................... 6

......................................... 44

2.8

Reset and Power Down

............................. 7

8.1

.................................. 50

2.9

Power and Bias Connections

........................ 7

8.2

Cable Diagnostic Control Register (CDCR)

........ 74

2.10

Fiber Interface

....................................... 7

8.3

PHY Reset Control Register (PHYRCR)

........... 75

Hardware Configuration

............................... 8

8.4

Multi LED Control register (MLEDCR)

............. 75

8.5

IEEE1588 Precision Timing Pin Select (PTPPSEL)

3.1

Bootstrap Configuration

.............................. 8

...................................................... 75

3.2

Power Supply Configuration

........................ 10

8.6

IEEE1588 Precision Timing Configuration

3.3

IO Pins Hi-Z State During Reset

................... 12

(PTPCFG)

.......................................... 76

3.4

Auto-Negotiation

.................................... 12

8.7

Fiber Mode Control Register (FIBCR)

.............. 76

3.5

Auto-MDIX

.......................................... 13

8.8

TX_CLK Phase Shift Register (TXCPSR)

.......... 76

3.6

PHY Address

....................................... 13

8.9

Power Back Off Control Register (PWRBOCR)

.... 77

3.7

MII Isolate Mode

.................................... 14

8.10

Voltage Regulator Control Register (VRCR)

....... 77

3.8

Software Strapping Mode

.......................... 14

8.11

Fiber Mode Control Register 2 (FIBCR2)

.......... 77

3.9

LED Interface

....................................... 16

8.12

Fiber Mode Control Register 3 (FIBCR3)

.......... 78

3.10

Multi-Configurable LED (MLED)

.................... 17

8.13

Cable Diagnostic Configuration/Result Registers

.. 78

3.11

Loopback Functionality

............................. 17

Electrical Specifications

............................. 84

3.12

BIST

................................................ 19

9.1

ABSOLUTE MAXIMUM RATINGS

................. 84

3.13

Cable Diagnostics

.................................. 20

9.2

RECOMMENDED OPERATING CONDITIONS

.... 84

Interfaces

................................................ 21

9.3

48-Pin Industrial Device Thermal Characteristics

.. 84

4.1

Media Independent Interface (MII)

................. 21

9.4

48-Pin Extended Temperature (125°C) Device

4.2

Reduced Media Independent Interface (RMII)

..... 22

Thermal Characteristics

............................ 85

4.3

Serial Management Interface

....................... 24

9.5

DC CHARACTERISTICS, VDD_IO

................ 85

Architecture

............................................. 28

9.6

DC CHARACTERISTICS, SD_IN

.................. 85

5.1

100Base-TX Transmit Path

......................... 28

9.7

DC CHARACTERISTICS

........................... 85

5.2

100Base-TX Receive Path

......................... 31

9.8

Power Supply Characteristics

...................... 87

5.3

10Base-T Receive Path

............................ 33

9.9

AC Specifications

................................... 88

5.4

Auto Negotiation

.................................... 34

Revision History, Revision A

........................... 103

5.5

Link Down Functionality

............................ 36

Revision History, Revision B

........................... 103

5.6

100BaseX Fiber Mode

.............................. 37

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Pin Descriptions

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