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TLK111 Datasheet(PDF) 51 Page - Texas Instruments |
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TLK111 Datasheet(HTML) 51 Page - Texas Instruments |
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51 / 110 page ![]() TLK111 www.ti.com SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014 Table 8-4. Basic Mode Control Register (BMCR), address 0x0000 (continued) BIT BIT NAME DEFAULT DESCRIPTION 11 IEEE Power 0, RW Power Down: Down 1 = Enables IEEE power down mode 0 = Normal operation Setting this bit powers down the PHY. Only minimal register functionality is enabled during the power down condition. To control the power down mechanism, this bit is ORed with the input from the INT/PWDN pin. When the active low INT/PWDN is asserted, this bit is set. 10 Isolate 0, RW Isolate: 1 = Isolates the Port from the MII with the exception of the serial management 0 = Normal operation 9 Restart Auto- 0, RW/SC Restart Auto-Negotiation: Negotiation 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto- Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit. 0 = Normal operation Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it self-clears. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit. 8 Duplex Mode 1, Pin_Strap, Duplex Mode: SWSC_Strap, When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be RW selected. 1 = Full Duplex operation led control 0 = Half Duplex operation 7 Collision Test 0, RW Collision Test: 1 = Collision test enabled 0 = Normal operation When set, this bit causes the COL signal to be asserted in response to the assertion of TX_EN within 512 bit times. The COL signal is de-asserted within 4 bit times in response to the de-assertion of TX_EN. 6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0. Copyright © 2013–2014, Texas Instruments Incorporated Register Block 51 Submit Documentation Feedback Product Folder Links: TLK111 |
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