TLK111 datasheet(67/110 Pages) TI1

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TLK111

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SLLSEF8B – AUGUST 2013 – REVISED JANUARY 2014

Table 8-20. PHY Specific Control Register (PHYSCR), address 0x0011 (continued)

BIT

NAME

DEFAULT

DESCRIPTION

Scrambler

0,RW

Scrambler Bypass:

Bypass

1 = Scrambler bypass enabled

0 = Scrambler bypass disabled

RESERVED

0, RO

RESERVED: Writes ignored, read as 0.

9:8

Loopback

01,RW

Far-End Loopback FIFO Depth:

FIFO Depth

00 = 4 nibbles FIFO

01 = 5 nibbles FIFO

10 = 6 nibbles FIFO

11 = 8 nibbles FIFO

This FIFO is used to adjust RX (recovered) clock rate to TX clock rate. FIFO depth need to be set

based on expected maximum packet size and clock accuracy. Default value sets to 5 nibbles.

7:5

RESERVED

000, RO

RESERVED: Writes ignored, read as 0.

COL FD

0, RW

Collision in Full-Duplex Mode:

Enable

1 = Enable generating Collision signaling in Full Duplex

0 = Disable Collision indication in Full Duplex mode. Collision will be active in Half Duplex only.

INT POL

1,RW

Interrupt Polarity:

1 = Steady state (normal operation) is 1 logic and during interrupt is 0 logic.

0 = Steady state (normal operation) is 0 logic and during interrupt is 1 logic.

tint

0,RW

Test Interrupt:

1 = Generate an interrupt

0 = Do not generate interrupt

Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be

generated as long as this bit remains set.

INT_EN

0,RW

Interrupt Enable:

1 = Enable event based interrupts

0 = Disable event based interrupts

Enable interrupt dependent on the event enables in the MISR register (0x0012).

INT_OE

0,RW

Interrupt Output Enable:

1 = INT / PWDN is an Interrupt Output

0 = INT / PWDN is a Power Down

Enable active low interrupt events via the INT / PWDN pin by configuring the INT / PWDN pin as an

output.

8.1.17 MII Interrupt Status Register 1 (MISR1)

This register contains events status and enables for the interrupt function. If an event has occurred since

the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the

0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt

is not enabled.

Table 8-21. MII Interrupt Status Register 1 (MISR1), address 0x0012

BIT

NAME

DEFAULT

DESCRIPTION

15:14

RESERVED

00, RO

RESERVED: Writes ignored, read as 0.

Link Status Changed INT

0,RO, COR

Change of Link Status interrupt:

1 = Change of link status interrupt is pending

0 = No change of link status

Speed Changed INT

0,RO, COR

Change of Speed Status interrupt:

1 = Change of speed status interrupt is pending

0 = No change of speed status

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