82503 datasheet(8/45 Pages) INTEL

8 / 45 page

82503

26 Mode Pins

Symbol

PLCC

QFP

Type

Name and Function

TPEAUI

PORT SELECT

TTL inputLED output If APORT is low

TPEAUI is an input and selects either the TPE port (TPEAUI

high) or AUI port (TPEAUI low) If APORT is high the 82503 will

indicate the port selected by driving TPEAUI high (TPE) or low

(AUI) TPEAUI can drive an LED pull-up

APORT

AUTOMATIC PORT SELECTION

TTL input When high 82503

will automatically select TPE or AUI port based on presence of

valid link beats or frames on the TPE receive input Mode

selected will be indicated on TPEAUI

APOLXSQ

AUTOMATIC POLARITY CORRECTIONEXTENDED

SQUELCH ENABLE

TTL input When high the extended

squelch mode is disabled and automatic polarity correction is

enabled Both junctions (APOL and XSQ) are enabled when this

pin is at a high impedance state When low both functions

become disabled The presence of a polarity fault on the TPE

receive pair is indicated on POLED regardless of the state of

APOL

LID

LINK INTEGRITY DISABLE

TTL input If high link integrity

function is disabled If low link integrity function is enabled

CS0

CONTROLLER SELECT

Selects the appropriate interface for

the desired Ethernet controller When CS01 e 00 supports

CS1

Intel controllers When CS01 e 01 supports Fujitsu

controllers When CS01 e 10 supports Western Digital and

National controllers When CS01 e 11 supports AMD

controllers (See Table 2)

LPBK

LOOPBACK

TTL input An active low input signal that causes

the 82503 to enter diagnostic loopback mode The twisted pair

or AUI medium will be removed from the circuit thus isolating

the node from the network When not connected this pin

assumes the inactive (high) state Diagnostic loopback does not

disable the operation of the link integrity processor link beat

generator or automatic port selection

JABD

JABBER DISABLE

TTL input When high this pin disables the

jabber function When low the jabber function is enabled and

the device performs AUI or TP jabber protection for the active

port If this pin and TEST are asserted during a falling edge of

RESET the 82503 enters its low power mode when either this

pin or TEST deasserts then the 82503 transitions to its normal

operating mode

TEST

TEST MODE ENABLE

TTL input When TEST is high and

RESET is deasserted a customer test mode is directly

accessed When driven low test mode is disabled If this pin and

JABD are asserted during a falling edge of RESET the 82503

enters its low power mode when either this pin or JABD

deasserts then the 82503 transitions to its normal operating

mode

RESET

TTL input When high resets internal circuitry On the

falling edge of RESET either test mode or low power mode can

be entered depending on the state of JABD and TEST

82503 Datasheet(PDF) 8 Page - Intel Corporation

82503 Datasheet(HTML) 8 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL