82503 datasheet(16/45 Pages) INTEL

16 / 45 page

82503

Table 2 Controller Interface Selection

Intel

National WD

AMD

Fujitsu

82503

Controller

Controllers

Controller

Controllers

825XX

8390 83C690

7990 (LANCE)

86950 (Etherstar)

83832 (SONIC)

79C900 (ILACC)

CS0(1)

CS1

Sense

TxC

Low

TXC

High

TCLK

High

TCKN

Low

TxD

High

TXD

High

TXD

High

RTS

Low

TXE

High

TENA

High

TEN

High

RxC

Low

RXC

High

RCLK

High

RCKN

Low

RxD

High

RXD

High

RXD

High

CRS

Low

CRS

High

RENA

High

XCD

High

CDT

Low

COL

High

CLSN

High

XCOL

Low

LPBK

Low

LPBK

High

LPBK

High

(Note 2)

NOTES

1 CS0 and CS1 are intended to be static pins only Switching CS0 and CS1 during network reception or transmission will

produce unpredictable results

2 Refer to Section 312

RESET LOW-POWER AND

TEST MODES

41 Reset

When RESET is asserted the device resets its inter-

nal circuits RESET is required after power up and

before data can be transmitted or received It is al-

lowed any time thereafter but any existing receive or

transmit activity will be lost and all state machines

(Link integrity Jabber and Polarity Correction) re-

turn to their initial states TEST must be held low for

a device reset to prevent entering a test for low pow-

er mode During RESET TxC continues without in-

terruption (in Fujitsu mode both TxC and RxC run

continuously)

42 Low Power and High Impedance

Modes

When RESET is deasserted while both TEST and

JABD are held high the 82503 enters its low power

and high impedance modes The majority of internal

circuitry is powered down and many inputs and out-

puts are three-stated

These pins are

APORT

APOLXSQ LID TPEAUI POLED LILED RTS

LPBK RxD TxD CRS and CDT When either JABD

or TEST is deasserted the device begins a power

on cycle which lasts less than 1 ms During this cy-

cle all inputs are ignored and all transmissions are

disabled If RTS is active when the device returns to

normal operation the remainder of that packet frag-

ment is not transmitted Normal transmissions are

resumed at the start of the first complete data pack-

43 Diagnostic Loopback

This is a diagnostic test mode to help in fault isola-

tion and detection Serial NRZ data input on TxD is

Manchester encoded and then looped back through

the Manchester decoder (TMD) appearing at the

RxD output Collision detect is asserted following

each transmission to simulate the SQE test Output

cable drivers and input amplifiers are disconnected

from the controller interface pins while in this mode

The link integrity and polarity fault detection func-

tions are not inhibited by diagnostic loopback mode

If otherwise enabled they continue to function

44 Customer Test Mode

(Continuous AUITPE Transmit)

In this mode the 82503 continuously transmits data

without the intervention of a LAN controller Trans-

mission is at 10 MHz (11-bit pattern) and can occur

on either the TPE or AUI port The jabber timer is

disabled in this mode allowing users to easily test

the 10BASE-T harmonic content specification and

the quality of their analog front end design without

complex software exercisers

Customer Test Modeand Low Power Mode are se-

lected at the deassertion of RESET as shown in the

following table (Note that the 82503 must be in non-

loopback mode before it can enter the customer test

mode)

82503 Datasheet(PDF) 16 Page - Intel Corporation

82503 Datasheet(HTML) 16 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL