82802AB datasheet(22/53 Pages) INTEL

22 / 53 page

Intel

® 82802AB/AC Firmware Hub

Datasheet

4.5.

Block Erase Command

The erase command operates on one block at a time. This command requires an (arbitrary) address

within the block to be erased. Recall that erasure changes all block data to FFh. Block preconditioning,

erase, and erase verify are handled internally by the WSM, which is transparent to the system. After

issuing the erase command, the device automatically outputs status register data when read. When the

block erase completes, the status register may be checked. If the FWH detects a block erase error, the

status register should be cleared before system software attempts corrective actions. After a block erase,

the CUI remains in read status register mode until a new command is issued.

Successful block erasure requires that the corresponding block’s write-lock-bit is cleared, and the

corresponding write-protect pin (TBL# or WP#) is inactive. If a block erase is attempted when the block

is locked, the block erase will fail, with the reason for failure in the status register.

Successful block erase only occurs when VPP = VPPH1 or VPPH2. If the erase operation is attempted at

≠≠≠≠ VPPH1 or VPPH2, erratic results may occur.

4.6.

Program Command

Program command operates on one byte at a time. This command specifies the address and data to be

programmed. After the CUI receives the command, the WSM takes over, controlling the program and

verify algorithms internally. After the program command is written, the device automatically outputs the

status register data when read. When programming is complete, the status register may be checked. If a

program error is detected, the status register should be cleared before corrective action is taken by the

software. The internal WSM verification error checking only detects 1s that does not successfully

program to 0s. The CUI remains in read status register mode until it receives another command.

Reliable programming only occurs when VPP = VPPH1 or VPPH2. If programming is attempted at

≠≠≠≠ VPPH1 or VPPH2, erratic results may occur.

Successful program operation also requires that the corresponding block’s write-lock bit be cleared and

that the corresponding write-protect pin (TBL# or WP#) be inactive. If program operation is attempted

when the block is locked, the operation will fail.

82802AB Datasheet(PDF) 22 Page - Intel Corporation