82802AB datasheet(43/53 Pages) INTEL

43 / 53 page

Intel

® 82802AB/AC Firmware Hub

Datasheet

Clock

Cycle

Field

Name

Field Contents

FWH[3:0]

Direction

Comments

TAR0

1111

OUT

then float

In this clock cycle, the FWH has driven the bus to all

1s and then floats the bus prior to the next clock

cycle. This is the first part of the bus “turnaround

cycle.”

TAR1

1111 (float)

Float then

The master (Intel ICH) resumes control of the bus

during this cycle.

Note:

1. Field contents are valid on the rising edge of the present clock cycle.

5.4.1.4.

Write Waveforms

Figure 11.

Write Waveforms

IMADDR

STR

CLK

FWH[3:0]

FWH4

IDS

IMS

TAR

SYN

DATA

TAR

5.4.1.5.

Response To Invalid Fields

During FWH operations, the Intel FWH will not explicitly indicate that it has received invalid field

sequences. The response to specific invalid fields or sequences is as follows:

• Address out of range: The Intel FWH address sequence is 7 fields long (28 bits), but only the last

five address fields (20 bits) will be decoded by an 8-Mbit FWH. (For a 4-Mbit density, the most-

significant bit (FWH3) in the third address field also will be ignored.) The Intel FWH will respond

to these lower addresses, regardless of the value of the more-significant address bits. Address A22

has the special function of directing reads and writes to the flash core (A22 = 1) or to the register

space (A22 = 0).

• Invalid IMSIZE field: If the Intel FWH receives an invalid size field during a read or write

operation, the internal state machine will reset and no operation will be attempted. The Intel FWH

will generate no response of any kind in this situation. Invalid-size fields for a read cycle are

anything but 0000. Invalid-size fields for a write cycle are anything but 0000. When accessing

• Non-page-aligned address: The Intel FWH assumes that multibyte read addresses are page aligned

(i.e., for a 32-byte access, the lower 5 address bits will be zero). If they are not zero, the first byte

of data returned by the Intel FWH will correspond to that explicit address, and subsequent data will

be as if the first address was indeed page aligned.

Once valid START, IDSEL, and IMSIZE fields are received, the Intel FWH always will respond to

subsequent inputs as if they were valid. As long as the states of FWH [3:0] and FWH4 are known, the

response of the Intel FWH to signals received during the FWH cycle should be predictable. The Intel

FWH will make no attempt to check the validity of incoming flash operation commands.

82802AB Datasheet(PDF) 43 Page - Intel Corporation

82802AB Datasheet(HTML) 43 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL