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82802AB Datasheet(PDF) 47 Page - Intel Corporation |
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82802AB Datasheet(HTML) 47 Page - Intel Corporation |
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47 / 53 page ![]() Intel ® 82802AB/AC Firmware Hub R Datasheet 47 6. PROM Programming Specifications 6.1. Programming (“A/A Mux”) Mode Operation The Intel® 82802 is designed to offer a parallel programming mode for faster factory programming. This mode, called the A/A Mux mode, is selected by IC high. The IC pin is pulled down internally in the Intel® 82802, so it should be expected that a modest current will be drawn. (See the pin descriptions in Table 1 for further information.) The following information applies only to the Intel® 82802 when in the A/A Mux mode. Information regarding the FWH mode (i.e., the standard operating mode) is provided in earlier chapters of this document 6.2. Bus Operation All A/A mux bus cycles can be conformed to operate on most automated test equipment and PROM programmers. 6.2.1. Output Disable/Enable With OE# at the logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ7 are placed in the high-impedance state. With OE# at the logic-low level (VIL), the device outputs are enabled. Output pins DQ0–DQ7 are placed in the output-drive state. 6.2.2. Row/Column Addresses R/C# is the A/A mux control pin used to latch row (A0–A10) and column addresses (A11–A18/4 Mbits, or A[11:19] /8 Mbits). R/C# latches row addresses on the falling edge and column addresses on the rising edge. 6.2.3. Read Operation Block information, identifier codes or status register data can be read independently of the VPP voltage. The first task is to write the appropriate read-mode command (Read Array, Read Identifier Codes or Read Status Register) to the CUI. Upon initial device power-up or after exit from reset, the device defaults to the read array mode. Four control pins dictate the data flow into and out of the component: R/C#, OE#, WE#, and RST#. R/C# is the A/A mux control pin used to latch row and column addresses. OE#, the data output control pin (DQ0–DQ7), drives the selected memory data onto the I/O bus, when active. WE# and RST# must be at VIH. |
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