TSI721 datasheet(14/68 Pages) IDT

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1. Device Overview > Block Diagram

Tsi721 Datasheet

May 5, 2014

Formal Status

This document is confidential and is subject to an NDA.

Integrated Device Technology

1.3

Block Diagram

The Tsi721 block diagram is displayed in the following figure. The five main functions of the device are briefly described below.

Figure 1: Block Diagram

1.3.1

PCIe Interface

The PCIe Interface performs all the physical, data link, and transport layer protocols associated with PCIe.

1.3.2

S-RIO Interface

The S-RIO Interface performs all the physical and transport layer protocols associated with S-RIO.

1.3.3

Messaging Engine

The Messaging Engine uses S-RIO messaging logical layer functions with dedicated messaging DMA channels per Tx queue

and per Rx queue.

1.3.4

Mapping Engine

The Mapping Engine maps between PCIe and S-RIO transactions, including segmentation and reassembly as required.

1.3.5

Block DMA Engine

The Block DMA Engine uses 8 DMA channels, where descriptors of each DMA channel can perform read or write.

JTAG

I2C

GPIO

Clock

Reset

Block DMA Engine (BDMA)

Messaging Engine (SMSG)

PCIe

Gen2

Interface

(x4, x2, x1)

S-RIO

Gen2

Interface

(x4, x2, x1)

Mapping Engine

PCIe to S-RIO (PC2SR)

S-RIO to PCIe (SR2PC)

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