LM5037

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SNVS578D – NOVEMBER 2008 – REVISED MAY 2015

Feature Description (continued)

another value small enough to ensure the sync pulse width at RT1/SYNC is less than 60% of the clock period

under all conditions. When the synchronizing pulse transitions from low-to-high (rising edge), the voltage at the

RT1/SYNC pin must be driven to exceed 3.0 V from its nominal 2.0 Vdc level. During the synchronization clock

resistors are always required, whether the oscillator is free running or externally synchronized.

7.3.12 Gate Driver Outputs (OUTA and OUTB Pins)

The LM5037 device provides two alternating gate driver outputs, OUTA and OUTB. The internal gate drivers can

each source and sink 1.2-A peak each. The maximum duty cycle is inherently limited to less than 50% and is

7.3.13 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event the maximum rated

junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low power

standby state with the output drivers (OUTA and OUTB) and the bias regulators (VCC and REF) disabled. This

helps to prevent catastrophic failures from accidental device overheating. During thermal shutdown, the soft-start

capacitor is fully discharged and the controller follows a normal start-up sequence after the junction temperature

falls to the operating level (140°C).

7.4 Device Functional Modes

7.4.1 Overload Protection Timer

The LM5037 device provides a current limit restart timer to disable the outputs and force a delayed restart

(hiccup mode) if a current limit condition is repeatedly sensed. The number of cycle-by-cycle current limit events

required to trigger the restart is programmed by the external capacitor at the RES pin. During each PWM cycle,

the device either sources to or sinks current from the RES pin capacitor. If no current limit is detected during a

cycle, a 8-µA discharge current sink is enabled to pull the RES pin towards ground. If a current limit is detected,

the 8-µA sink current is disabled and a 18-µA current source causes the voltage at the RES pin to gradually

increase. The device protects the converter with cycle-by-cycle current limiting while the voltage at RES pin

increases. If the RES voltage reaches the 2.0 V threshold, the following restart sequence occurs (also see

Figure 16):

•

The RES capacitor and SS capacitors are fully discharged.

•

The soft-start current source is reduced from 100 µA to 1 µA.

•

The SS capacitor voltage slowly increases. When the SS voltage reaches approximately 1 V, the PWM

comparator produces the first narrow output pulse. After the first pulse occurs, the SS source current reverts

to the normal 100 µA level. The SS voltage increases at its normal rate, gradually increasing the duty cycle of

the output drivers.

•

If the overload condition persists after restart, cycle-by-cycle current limiting begins to increase the voltage on

the RES capacitor again, repeating the hiccup mode sequence.

•

If the overload condition no longer exists after restart, the RES pin remains at ground by the 8-µA current sink

and normal operation resumes.

7.4.1.1 Overload Timer Function

This section lists the modes of protection available by configuring the overload timer function.

7.4.1.1.1

Cycle-by-cycle Only

The hiccup mode can be completely disabled by connecting a zero to 50 k

Ω resistor from the RES pin to AGND.

In this configuration, the cycle-by-cycle protection limits the output current indefinitely and no hiccup sequences

occurs.

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