UCC24636DBVT datasheet(15/35 Pages) TI1

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VPC BLK

TBLK

100 ns

18 pF

VSC2

OUT(max)

VSC1

VSC2

2.2 V

VSC2

OUT(min)

VSC1

VSC2

0.3V

UCC24636

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SLUSCG2A – MARCH 2016 – REVISED MARCH 2016

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Feature Description (continued)

The operating voltage on the VSC pin should be within the range of 0.3 V < VVSC < 2.2 V. Referring to Figure 7, if

VVSC is greater than 2.3 V, the linear dynamic range is exceeded and RatioVPC_VSC is increased; in this condition

the DRV on time is more than expected, resulting in possible negative current conduction. To ensure the VSC

voltage is within range, confirm with Equation 4 and Equation 5.

(4)

where

•

VOUT(min) is the minimum converter output operating voltage of the SR controller.

•

VOUT(max) is the maximum converter output operating voltage of the voltage at OVP.

(5)

Discrimination of ringing during DCM operation from valid primary on-time is achieved by a dynamic VPC rising

threshold and programmable blanking time. The dynamic threshold VVPC-TH is 85% typical ratio of the previous

VPC pin peak voltage. Referring to Figure 13, the VPC pin voltage is sampled after the VPC voltage is greater

than VVPCEN and VVPC-TH for t > tVPC-BLK. The function of the dynamic threshold VVPC-TH is to reject the ringing in

DCM operation from the primary conduction pulses. The dynamic threshold has an active range from the

minimum VVPCEN voltage to a maximum of 1-V clamp. The blanking time is programmable from 200 ns to 2 µs in

order to accommodate a variety of converter designs.

Refer to Figure 16 for guidance on selecting the blanking time. The blanking time should be selected as long as

reasonable and still accommodate the minimum primary on-time at light-load condition and high-line voltage. In

the high-line minimum load condition, select a blanking time that meets the following criteria (Equation 6) to

accommodate tolerance of the blanking time and the tVPC-SPL sampling time window.

tVPC-BLK = (tPRI x 0.85) – 120 ns

(6)

For rejection of DCM ringing, the blanking time should be longer than the time that the ring is above the VVPC-TH

dynamic threshold, which is 85% of the minimum SR VDS peak voltage. Determine these criteria at low line and

maximum load condition. It is recommended that the transformer turns ratio be selected such that the secondary

reflected voltage is < 85% of VIN(min) bulk capacitor voltage at the highest load when DCM operation occurs at the

low line input condition.

To determine the resistor value for tVPC-BLK use Equation 7 to select from a range of 200 ns to 2 µs.

where

•

tVPC-BLK is the target blanking time.

(7)

Additional discrimination for proper SR timing control is provided by the tOFF function. Refer to Figure 13 for the

timing details. After the DRV turn off, the DRV is inhibited from turning on again until the tOFF timer expires. This

protects against SR false turn on from SR VDS DCM ringing below ground.

UCC24636DBVT Datasheet(PDF) 15 Page - Texas Instruments

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