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DP83266VF Datasheet(PDF) 47 Page - National Semiconductor (TI) |
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DP83266VF Datasheet(HTML) 47 Page - National Semiconductor (TI) |
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47 / 152 page  70 Control Information (Continued) TABLE 7-5 MAC Event Registers Addr Name D7 D6 D5 D4 D3 D2 D1 D0 Read Write 008 MCCMP MCCMP(7 – 0) Always Always 009 – 00B Reserved RES RES RES RES RES RES RES RES NA NA 00C CRS0 RFLG RS2 RS1 RS0 RES RTS2 RTS1 RTS0 Always Ignored 00D Reserved RES RES RES RES RES RES RES RES NA NA 00E CTS0 ROP TS2 TS1 TS0 TTS3 TTS2 TTS1 TTS0 Always Ignored 00F Reserved RES RES RES RES RES RES RES RES NA NA 010 RELR0 RES DUP ADD PINV OTR MAC CLMR BCNR RNOP ROP Always Conditional 011 REMR0 RES DUP ADD PINV OTR MAC CLMR BCNR RNOP ROP Always Always 012 RELR1 LOCLM HICLM MYCLM RES RES RES MYBCN OTRBCN Always Conditional 013 REMR1 LOCLM HICLM MYCLM RES RES RES MYBCN OTRBCN Always Always 014 TELR0 RLVD TKPASS TKCAPT CBERR DUPTKR TRTEXP TVXEXP ENTRMD Always Conditional 015 TEMR0 RLVD TKPASS TKCAPT CBERR DUPTKR TRTEXP TVXEXP ENTRMD Always Always 016 – 017 Reserved RES RES RES RES RES RES RES RES NA NA 018 CILR RES TK RCVD FR TRX FR NCOP FR COP FR LST FREI FR RCV Always Conditional 019 CIMR RES TK RCVD FR TRX FR NCOP FR COP FR LST FREI FR RCV Always Always 01A – 01B Reserved RES RES RES RES RES RES RES RES NA NA 01C COLR RES TK RCVD FR TRX FR NCOP FR COP FR LST FREI FR RCV Always Conditional 01D COMR RES TK RCVD FR TRX FR NCOP FR COP FR LST FREI FR RCV Always Always 01E – 027 Reserved RES RES RES RES RES RES RES RES NA NA 028 IELR RES RES RES RES TSM ERR RSM ERR RES MPE Always Conditional 029 – 02B Reserved RES RES RES RES RES RES RES RES NA NA 02C ESR CWI CCE CPE RES RES RES RES PPE Always Conditional 02D EMR ZERO CCE CPE RES RES RES RES PPE Always Always 02E ICR ESE IERR RES RES COE CIE TTE RNG Always Ignored 02F IMR ESE IERR RES RES COE CIE TTE RNG Always Always 030 – 03F Reserved RES RES RES RES RES RES RES RES NA NA Note 1 Attempts to access reserved locations within the MAC Event Registers will result in Command Rejects (ESRCCE set to ONE) Note 2 Bits in the conditional write registers are only written when the corresponding bit in the Compare Register is equal to the bit to be overwritten Note 3 On Master Reset all Event Registers are reset to Zero 73 ACCESS RULES For the Ring Engine (MAC) all Control Interface accesses are checked against the current operational mode to deter- mine if the register is currently accessible If not currently accessible the Control Bus Interface access is rejected (and reported in an Event Register) This means that the Control Bus Interface completes all accesses in a determi- nistic amount of time Certain Status and Parameter regis- ters are not accessible while in Run mode because the Ring Engine might access those locations The Exception Status Register can be checked to verify that the operation terminated normally The Service Engine Registers are always accessible 731 MAC Parameter RAM The MAC parameter RAM is accessible in Stop mode and in RUN mode while the MAC Transmitter is in states T0 T1 or T3 OptionITC and OptionIRR are set and FunctionBCN and FunctionCLM are not set Otherwise a command reject is given (ESRCCE) and the Parameter RAM will not be read or written 47 |
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