DP83256 datasheet(55/146 Pages) TI1

55 / 146 page

50 Registers (Continued)

510 RECEIVE CONDITION REGISTER A (RCRA)

The Receive Condition Register A maintains a historical record of the Line States recognized by the Receiver Block

When a new Line State is entered the bit corresponding to that line state is set to 1 The bits corresponding to the previous Line

States are not cleared by the PLAYERa device thereby maintaining a record of the Line States detected

The Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR) will be set to 1 when one or more bits within the

Receive Condition Register A is set to 1 and the corresponding mask bit(s) in Receive Condition Mask Register A (RCMRA) is

also set to 1

ACCESS RULES

ADDRESS

READ

WRITE

09h

Always

Conditional

LSUPI

LSC

NLS

MLS

HLS

QLS

NSD

Bit

Symbol

Description

NSD

NO SIGNAL DETECT

Indicates that the Signal Detect pin (TTLSD) has been deasserted and that the Clock

Recovery Module is not receiving data from the PMD receiver

QLS

QUIET LINE STATE

Received a minimum of eight consecutive Quiet symbol pairs (00000 00000)

HLS

HALT LINE STATE

Received a minimum of eight consecutive Halt symbol pairs (00100 00100)

MLS

MASTER LINE STATE

Received a minimum of eight consecutive Halt-Quiet symbol pairs (00100 00000)

NLS

NOISE LINE STATE

Detected a minimum of sixteen noise events

NOISE THRESHOLD

This bit is set to 1 when the internal Noise Counter reaches 0 It will remain set until a value

equal to or greater than one is loaded into the Noise Threshold Register or Noise Prescale Threshold Register

During the reset process (ie ERSTeGND) since the Noise Counter is initialized to 0 the Noise Threshold bit will

be set to 1

LSC

LINE STATE CHANGE

A line state change has been detected

LSUPI

LINE STATE UNKNOWN AND PHY INVALID

The Receiver Block has not detected the minimum conditions to

enter a known line state

In addition the most recently known line state was one of the following line states No Signal Detect Quiet Line

State Halt Line State Master Line State or Noise Line State

DP83256 Datasheet(PDF) 55 Page - Texas Instruments

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