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DP83256 Datasheet(PDF) 11 Page - Texas Instruments

Part # DP83256
Description  PLAYER(TM) Device (FDDI Physical Layer Controller)
PDF  146 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DP83256 Datasheet(HTML) 11 Page - Texas Instruments

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30 Functional Description (Continued)
Framing may be temporarily suspended (ie framing hold)
in order to maintain data integrity
Detecting JK
The JK symbol pair can be used to detect the beginning of a
frame during Active Line State (ALS) and Idle Line State
(ILS) conditions
While the Line State Detector indicates Idle Line State the
receiver ‘‘reframes’’ upon detecting a JK symbol pair and
enters the Active Line State
During Active Line State acceptance of a JK symbol (re-
framing) is allowed for any on-boundary JK which is detect-
ed at least 15 byte times after the previous JK
During Active Line State once reframed on a JK a subse-
quent off-boundary JK is ignored even if it is detected be-
yond 15 byte times after the previous JK
During Active Line State an Idle or Ending Delimiter (T)
symbol will allow reframing on any subsequent JK if a JK is
detected at least 15 byte times after the previous JK
Detecting HALT-HALT AND HALT-QUIET
During Idle Line State the detection of a Halt-Halt or Halt-
Quiet symbol pair will still allow the reframing of any subse-
quent on-boundary JK
Once a JK is detected during Active Line State off-bounda-
ry Halt-Halt or Halt-Quiet symbol pairs are ignored until the
Elasticity Buffer (EB) has an opportunity to recenter They
are treated as violations
After recentering on a Halt-Halt or Halt-Quiet symbol pair
all off boundary Halt-Halt or Halt-Quiet symbol pairs are ig-
nored until the EB has a chance to recenter during a line
state other than Active Line State (which may be as long as
28 byte times)
SYMBOL DECODER
The Symbol Decoder is a two level system The first level is
a 5-bit to 4-bit converter and the second level is a 4-bit
symbol pair to byte-wide code converter
The first level latches the received 5-bit symbols and de-
codes them into 4-bit symbols Symbols are decoded into
two types data and control The 4-bit symbols are sent to
the Line State Detector and the second level of the Symbol
Decoder See Table 3-1 for the 5B4B Symbol Decoding
list
The second level translates two symbols from the 5B4B
converter and the line state information from the Line State
Detector into the National byte-wide code
LINE STATE DETECTOR
The ANSI X3T95 FDDI Physical Layer (PHY) standard
specifies eight Line States that the Physical Layer can
transmit These Line States are used in the Connection
Management process They are also used to indicate data
within a frame during normal operation
The Line States are reported through the Current Receive
State Register (CRSR)
Receive Condition Register A
(RCRA) and Receive Condition Register B (RCRB)
TABLE 3-1 5B4B Symbol Decoding
Symbol
Incoming 5B
Decoded 4B
0
11110
0000
1
01001
0001
2
10100
0010
3
10101
0011
4
01010
0100
5
01011
0101
6
01110
0110
7
01111
0111
8
10010
1000
9
10011
1001
A
10110
1010
B
10111
1011
C
11010
1100
D
11011
1101
E
11100
1110
F
11101
1111
I (Idle)
11111
1010
H (Halt)
00100
0001
JK (Starting
11000 and
1101
Delimiter)
10001
T (Ending
01101
0101
Delimiter)
R (Reset)
00111
0110
S (Set)
11001
0111
Q (Quiet)
00000
0010
V (Violation)
00001
0010
V
00010
0010
V
00011
0010
V
00101
0010
V
00110
0010
V
01000
0010
V
01100
0010
V
10000
0010
Note
V denotes PHY Invalid or an Elasticity Buffer stuff byte
I denotes Idle symbol in ILS or an Elasticity Buffer stuff byte
LINE STATES DESCRIPTION
Active Line State
The Line State Detector recognizes the incoming data to be
in the Active Line State upon the reception of the Starting
Delimiter (JK symbol pair)
The Line State Detector continues to indicate Active Line
State while receiving data symbols Ending Delimiter (T
symbols) and Frame Status symbols (R and S) after the JK
symbol pair
Idle Line State
The Line State Detector recognizes the incoming data to be
in the Idle Line State upon the reception of 2 Idle symbol
pairs nominally (plus up to 9 bits of 1 in start up cases)
Idle Line State indicates the preamble of a frame or the lack
of frame transmission during normal operation Idle Line
State is also used in the handshake sequence of the PHY
Connection Management process
10



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