DP83256 datasheet(77/146 Pages) TI1

77 / 146 page

50 Registers (Continued)

532 CMT CONDITION COMPARISON REGISTER (CMTCCR)

The CMT Condition Comparison Register (CMTCR) ensures that the Control Bus must first read a bit modified by the PLAYERa

device before it can be written to by the Control Bus Interface

The current state of the CMT Condition Register (CMTCR) is automatically written into the CMT Condition Comparison Register

(CMTCR) (ie CMTCCR e CMTCR) during a Control Bus Interface read-cycle of CMTCR

During a Control Bus Interface write cycle the PLAYERa device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Control Register (ICR) to 1 and disallow the setting or clearing of a bit within the CMTCR when the value of a bit in the CMTCR

differs from the value of the corresponding bit in the CMT Condition Comparison Register

ACCESS RULES

ADDRESS

READ

WRITE

1Fh

Always

TCOC

STEC

RES

Bit

Symbol

Description

D0-D5

RES

RESERVED

Reserved for future use

STEC

SCRUB TIMER EXPIRED COMPARISON

The comparison bit for the Scrub Timer Expire bit (STE) of the CMT

Condition Register (CMTCR)

TCOC

TRIGGER CONDITION OCCURRED COMPARISON

The comparison bit for the Trigger Condition Occurred

(TCO) bit of the CMT Condition Register (CMTCR)

DP83256 Datasheet(PDF) 77 Page - Texas Instruments