DP83256 datasheet(64/146 Pages) TI1

64 / 146 page

50 Registers (Continued)

519 STATE PRESCALE THRESHOLD REGISTER (SPTR)

The State Prescale Threshold Register contains the start value for the State Prescale Timer The State Prescale Timer is a down

counter It is used in conjunction with the State Timer to count the Line State duration

The threshold values for the State Timer and State Prescale Timer are simultaneously loaded into both timers if one of the

following conditions is true

1 Both the State Timer and State Prescale Timer reach zero and the current Line State is Halt Line State Idle Line State

Master Line State Quiet Line State or No Signal Detect

2 A Line State change occurs and the new Line State is Halt Line State Idle Line State Master Line State Quiet Line State or

No Signal Detect

3 The State Threshold Register or State Prescale Threshold Register goes through a Control Bus Interface write cycle

The State Prescale Timer will decrement every 80 ns if the current Line State is Halt Line State Idle Line State Master Line

State Quiet Line State or No Signal Detect

ACCESS RULES

ADDRESS

READ

WRITE

12h

Always

SPT7

SPT6

SPT5

SPT4

SPT3

SPT2

SPT1

SPT0

Bit

Symbol

Description

D0 – D7

SPT0 – SPT7

STATE PRESCALE THRESHOLD BIT k0–7l

Start value for the State Prescale Timer

SPT0 is the Least Significant Bit (LSB)

DP83256 Datasheet(PDF) 64 Page - Texas Instruments