DP83256 datasheet(96/146 Pages) TI1

96 / 146 page

60 Signal Descriptions (Continued)

62 DP83256VF-AP SIGNAL DESCRIPTIONS

The pin descriptions for the DP83256VF-AP are divided into five functional interfaces PMD Interface PHY Port Interface

Control Bus Interface Clock Interface and Miscellaneous Interface

For a Pinout Summary List refer to Table 8-2 and

Figure 8-2 DP83256VF-AP 100-Pin JEDEC Metric PQFP Pinout

PMD INTERFACE

The PMD Interface consists of IO signals used to connect the PLAYERa device to the Physical Medium Dependant (PMD)

sublayer

The DP83256VF-AP PLAYERa device actually has two PMD interfaces The Primary PMD Interface and the Alternate PMD

Interface

The Primary PMD Interface should be used for all PMD implementations that do not require an external scramblerdescrambler

function clock recovery function or clock generation function such as a Fiber Optic or Shielded Twisted Pair (SDDI) PMD The

second Alternate PMD Interface can be used to support Unshielded Twisted Pair (UTP) PMDs that require external scrambling

with no external clock recovery or clock generation functions required

Section 38 describes how the PLAYERa can be connected to the PMD and how the Alternate PMD can be enabled

Note that when the Alternate PMD Interface is not being used the pins that make up the interface must be connected in the

specific way described in the following Alternate PMD Interface table

Primary PMD Interface

Symbol

Description

PMIDa

PMD Indicate Data

Differential 100k ECL 125 Mbps serial data input signals from the PMD Receiver

into the Clock Recovery Module (CRM) of the PLAYERa

PMIDb

PMRDa

PMD Request Data

Differential 100k ECL 125 Mbps serial data output signals to the PMD transmitter

PMRDb

SDa

Signal Detect

Differential 100k ECL input signals from the PMD receiver indicating that a signal is being

received by the PMD receiver

SDb

DP83256 Datasheet(PDF) 96 Page - Texas Instruments