DP83256 datasheet(69/146 Pages) TI1

69 / 146 page

50 Registers (Continued)

524 USER DEFINABLE REGISTER (UDR)

The User Definable Register is used to monitor and control events which are external to the PLAYERa device

The value of the Sense Bits reflect the asserteddeasserted state of their corresponding Sense pins On the other hand the

Enable bits assertdeassert the Enable pins

Note

SB2 and EB2 are only effective for the DP83257

ACCESS RULES

ADDRESS

READ

WRITE

17h

Always

RES

EB2

RES

SB2

EB1

EB0

SB1

SB0

Bit

Symbol

Description

SB0

SENSE BIT 0

This bit is set to 1 if the Sense Pin 0 (SP0) is asserted (ie SP0eVCC) for a minimum amount of

time Once the asserted signal is latched Sense Bit 0 can only be cleared through the Control Bus Interface even

if the signal is deasserted This ensures that the Control Bus Interface will record the source of events which can

cause interrupts in a traceable manner

SB1

SENSE BIT 1

This bit is set to 1 if the Sense Pin 1 (SP1) is asserted (ie SP1eVCC) for a minimum amount of

time Once the asserted signal is latched Sense Bit 1 can only be cleared through the Control Bus Interface even

if the signal is deasserted This ensures that the Control Bus Interface will record the source of events which can

cause interrupts in a traceable manner

EB0

ENABLE BIT 0

The Enable Bit 0 allows control of external logic through the Control Bus Interface The User

Definable Enable Pin 0 (EP0) is asserteddeasserted by this bit

EP0 is deasserted (ie EP0eGND)

EP0 is asserted (ie EP0eVCC)

EB1

ENABLE BIT 1

This bit allows control of external logic through the Control Bus Interface The User Definable

Enable Pin 0 (EP0) is asserteddeasserted by this bit

EP1 is deasserted (ie EP1eGND)

EP1 is asserted (ie EP1eVCC)

SB2

SENSE BIT 2

This bit is set to 1 if the Sense Pin 2 (SP2) is asserted (ie SP2eVCC) for a minimum amount of

time Once the asserted signal is latched Sense Bit 2 can only be cleared through the Control Bus Interface even

if the signal is deasserted This ensures that the Control Bus Interface will record the source of events which can

cause interrupts in a traceable manner

Note

SB2 and EB2 are only effective for the DP83257

RES

RESERVED

Reserved for future use The reserved bit is set to 0 during the initialization process

(ie ERSTeGND)

Note

Users are discouraged from using this bit It may be set or cleared without any effects to the functionality of the PLAYERa device

EB2

ENABLE BIT2

The Enable Bit 2 allows control of external logic through the Control Bus Interface The User

Definable Enable Pin 2 (EP2) is asserteddeasserted by this bit

Note

SB2 and EB2 are only effective for the DP83257

EP2 is deasserted (ie EP2eGND)

EP2 is asserted (ie EP2eVCC)

RES

RESERVED

Reserved for future use The reserved bit is set to 0 during the initialization process

(ie ERSTeGND)

Note

Users are discouraged from using this bit It may be set or cleared without any effects to the functionality of the PLAYERa device

DP83256 Datasheet(PDF) 69 Page - Texas Instruments

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