DP83256 datasheet(59/146 Pages) TI1

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50 Registers (Continued)

514 NOISE THRESHOLD REGISTER (NTR)

The Noise Threshold Register contains the start value for the Noise Timer This threshold register is used in conjunction with the

Noise Prescale Threshold register for setting the maximum allowable time between entry to ILS HLS MLS ALS or NSD line

states The Noise timer is used to implement the TNE timing requirement of PCM The Noise timer decrements by one for every

80 x (NPTRa1) ns in case of Noise events As a result the internal noise counter takes the following amount of time to reach

zero

((NPTRa1) x NTR a NPTR) x 80 ns

The threshold values for the Noise Counter and Noise Prescale Counter are simultaneously loaded into both counters if one of

the following conditions is true

1 Both the Noise Counter and Noise Prescale Counter reach zero and the current Line State is either Noise Line State Active

Line State or Line State Unknown

2 The current Line State is either Halt Line State Idle Line State Master Line State Quiet Line State or No Signal Detect

3 The Noise Threshold Register or Noise Prescale Threshold Register goes through a Control Bus Interface write cycle

In addition the value of the Noise Prescale Threshold register is loaded into the Noise Prescale Counter if the Noise Prescale

Counter reaches zero

The Noise Counter and Noise Prescale Counter will continue to count without resetting or reloading the threshold values if a

Line State change occurs and the new line state is either Noise Line State Active Line State or Line State Unknown

When both the Noise Threshold Counter and Noise Counter both reach zero the Noise Threshold bit of the Receive Condition

The recommended default value for the NTR register is 40h and for the NPTR register is F9h which corresponds to 13 ms as

specified in the ANSI standard

ACCESS RULES

ADDRESS

READ

WRITE

0Dh

Always

RES

NT6

NT5

NT4

NT3

NT2

NT1

NT0

Bit

Symbol

Description

D0-D6

NT0-NT6

NOISE THRESHOLD BITk0-6l

Start value for the Noise Counter

NT0 is the Least Significant Bit (LSB)

RES

RESERVED

Reserved for future use

Note

Users are discouraged from using this bit Write data is ignored since the reserved bit is permanently set to 0

DP83256 Datasheet(PDF) 59 Page - Texas Instruments

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