DP83256 datasheet(75/146 Pages) TI1

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50 Registers (Continued)

530 RECEIVE CONDITION COMPARISION REGISTER B (RCCRB)

The Receive Condition Comparison Register B ensures that the Control Bus must first read a bit modified by the PLAYERa

device before it can be written to by the Control Bus Interface

The current state of RCRB is automatically written into the Receive Condition Comparison Register B (ie RCCRBeRCRB)

during a Control Bus Interface read cycle RCRB

During a Control Bus Interface write cycle the PLAYERa device will set the Conditional Write Inhibit bit (CWI) of the Interrupt

Condition Register (ICR) to 1 and prevent the setting or clearing of a bit within RCRB when the value of a bit in RCRB differs

from the value of the corresponding bit in the Receive Condition Comparison Register B

ACCESS RULES

ADDRESS

READ

WRITE

1Dh

Always

RESC

SILSC

EBOUC

CSEC

LSUPVC

ALSC

STC

ILSC

Bit

Symbol

Description

ILSC

IDLE LINE STATE COMPARISON

The comparison bit for the Idle Line State bit (ILS) of the Receive Condition

STC

STATE THRESHOLD COMPARISON

The comparison bit for the State Threshold bit (ST) of the Receive

Condition Register B (RCRB)

ALSC

ACTIVE LINE STATE COMPARISON

The comparison bit for the Active Line State bit (ALS) of the Receive

Condition Register B (RCRB)

LSUPVC

LINE STATE UNKNOWN AND PHY VALID COMPARISON

The comparison bit for the Line State Unknown and

PHY Valid bit (LSUPV) of the Receive Condition Register B (RCRB)

CSEC

CONNECTION SERVICE EVENT COMPARISON

CASCADE SYNCHRONIZATION ERROR

The comparison

bit for the Cascade Synchronization ErrorConnection Service Event bit (CSE) of the Receive Condition Register

B (RCRB)

EBOUC

ELASTICITY BUFFER OVERFLOW

UNDERFLOW COMPARISON

The comparison bit for the Elasticity Buffer

OverflowUnderflow bit (EBOU) of the Receive Condition Register B (RCRB)

SILSC

SUPER IDLE LINE STATE COMPARISON

The comparison bit for the Super Idle Line State bit (SILS) of the

Receive Condition Register B (RCRB)

RESC

RESERVED COMPARISON

The comparison bit for the Reserved bit (RES) of the Receive Condition Register B

(RCRB)

DP83256 Datasheet(PDF) 75 Page - Texas Instruments

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