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DP83256 Datasheet(PDF) 79 Page - Texas Instruments |
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DP83256 Datasheet(HTML) 79 Page - Texas Instruments |
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79 / 146 page  50 Registers (Continued) 534 CMT CONDITION MASK REGISTER (CMTCMR) This is the mask register for the CMT Condition Register (CMTCR) When the bits in both the CMTCMR and CMTCR are set the Receive Condition Register B’s Connection Service Event (RCRBCSE) bit will be set ACCESS RULES ADDRESS READ WRITE 21h Always Always D7 D6 D5 D4 D3 D2 D1 D0 TCOM STEM RES RES RES RES RES RES Bit Symbol Description D0-D5 RES RESERVED Reserved for future use D6 STEM SCRUB TIMER EXPIRED MASK The mask bit for the Scrub Timer Expired (STE) bit of the CMT Condition Register (CMTCR) D7 TCOM TRIGGER CONDITION OCCURRED MASK The mask bit for the Trigger Condition Occurred (TCO) bit of the CMT Condition Register (CMTCR) 78 |
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