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DP83256 Datasheet(PDF) 65 Page - Texas Instruments |
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DP83256 Datasheet(HTML) 65 Page - Texas Instruments |
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65 / 146 page  50 Registers (Continued) 520 CURRENT STATE COUNT REGISTER (CSCR) The Current State Count Register takes a snap-shot of the State Counter during every Control Bus Interface read cycle of this register During a Control Bus Interface write cycle the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) will be set to 1 and will ignore a write cycle ACCESS RULES ADDRESS READ WRITE 13h Always Write Reject D7 D6 D5 D4 D3 D2 D1 D0 SCLSCD CSC6 CSC5 CSC4 CSC3 CSC2 CSC1 CSC0 Bit Symbol Description D0 – D6 CSC0 – CSC6 CURRENT STATE COUNT BIT k0–6l Snapshot of the State Counter D7 SCLSCD STATE COUNTER LINE STATE CHANGE DETECTION 64 |
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