DP83256 datasheet(76/146 Pages) TI1

76 / 146 page

50 Registers (Continued)

531 MODE REGISTER 2 (MODE2)

The Mode Register 2 (MODE2) is used to configure the PLAYERa device

The register is used to software reset the chip setup data parity and enable scrubbing functions

Note

This register can not be written to during reset

ACCESS RULES

ADDRESS

READ

WRITE

1Eh

Always

Conditional

ESTC

RES

CLKSEL

RES

CBPE

PHYRST

Bit

Symbol

Description

PHYRST

PLAYER RESET

This bit can be used as a master software reset of the PLAYER function within the

PLAYERa device The clock distribution and recovery sections of the chip are not affected by this reset

The PLAYERa automatically clears this bit 32 byte time after its assertion to indicate that the reset action

has been completed

This bit can be set through a C-Bus write but can only be cleared by the PLAYERa

CBPE

C-Bus Parity Enable

This bit disables or enables parity checking on C-Bus data When this bit is set to 0 no

parity checking is done When the bit is set to 1 parity checking is enabled during a C-Bus write cycle Should

a mismatch occur the C-Bus Data Parity Error (ICRCPE) bit will be set and the corresponding C-Bus access

is discarded

C-Bus data parity is always generated during a C-Bus read cycle

D2 – D4

RES

RESERVED

Reserved for future use

CLKSEL

CLOCK SELECT

This bit controls the frequency of the CLK16 output It resets to 0 which sets the CLK16

output to a 15625 MHz frequency When set to 1 a 3125 MHz frequency is generated

Note

When the value of this bit is changed no glitches appear on the CLK16 output due to the frequency change

RES

RESERVED

Reserved for future use

ESTC

ENABLE SCRUBBING on TRIGGER CONDITIONS

When ESTC is set to 1 and a Trigger Condition occurs

(as set in the TDR register) the Trigger Transition Configuration Register (TTCR) is loaded into the

Configuration Register (CR) and scrubbing is started on all indicate ports that have changed

Scrubbing is accomplished by sending out 2 Phy

Invalid symbols followed by ‘‘scrub’’symbol pairs for a time

defined by the Scrub Timer Threshold register

DP83256 Datasheet(PDF) 76 Page - Texas Instruments

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