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DP83256 Datasheet(PDF) 120 Page - Texas Instruments

Part # DP83256
Description  PLAYER(TM) Device (FDDI Physical Layer Controller)
PDF  146 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DP83256 Datasheet(HTML) 120 Page - Texas Instruments

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70 Electrical Characteristics (Continued)
AC Characteristics for the Clock Interface Signals (Periods and Pulse Widths)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T2
LBC Period
80
ns
T9
LBC Pulse Width High
35
45
ns
T10
LBC Pulse Width Low
35
45
ns
T25
LSC Pulse Width High
12
19
ns
T26
LSC Pulse Width Low
21
28
ns
T27
CLK16 Period
MODE2CLKSEL e 064
ns
T28
CLK16 Pulse Width
MODE2CLKSEL e 027
32
37
ns
(Note 1)
T27
CLK16 Period
MODE2CLKSEL e 132
ns
T28
CLK16 Pulse Width
MODE2CLKSEL e 111
16
21
ns
(Note 1)
T29
REF
IN Pulse Width High
35
45
ns
Note 1
This parameter is not tested but is assured by correlation with characterization data
TLF11708 – 34
FIGURE 7-8 Clock Pulse Widths
AC Characteristics for Port A Interface and Port B Interface
The following signals are covered PHY Port A (AID AIP AIC ARD ARP ARC) and PHY Port B (BID BIP BIC BRD BRP
BRC)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
T30
LBC1 to Indicate Data Changes from
70
ns
TRI-STATE to Valid Data
T31
LBC1 to Indicate Data Changes from
70
ns
Active to TRI-STATE
T32
LBC1 to Indicate Data Sustain
9
ns
T33
LBC1 to Valid Indicate Data
45
ns
T34
Request Data to LBC1 Setup Time
15
ns
T35
Request Data to LBC1 Hold Time
3
ns
TLF11708 – 35
FIGURE 7-9 PHY Port Interface Timing
119



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