DS787PP9

16

5.10 Digital Switching Characteristics–Serial Control Port–SPI Master

Figure 5-4. Serial Control Port–SPI Slave Mode Timing

5.10 Digital Switching Characteristics–Serial Control Port–SPI Master Mode

port can be limited by the firmware application.

2. See Section 5.7.

3. SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter.

Parameter

Symbol Min

Typical

Max

Units

——

MHz

—

11*DCLKP+(SCP_CLK PERIOD)/2

—

ns

SCP_CLK low time

18

—

—

ns

SCP_CLK high time

18

—

—

ns

Setup time SCP_MISO input

9—

—

ns

Hold time SCP_MISO input

5—

—

ns

SCP_CLK low to SCP_MOSI output valid

——

8

ns

SCP_CLK low to EE_CS falling

7—

—

ns

SCP_CLK low to EE_CS rising

—

11*DCLKP+(SCP_CLK PERIOD)/2

—

ns

Bus free time between active EE_CS

—

3*DCLKP

—

ns

SCP_CLK falling to SCP_MOSI output high-Z

—

—

20

ns

SCP_BSY

SCP_CS

SCP_CLK

SCP_MOSI

SCP_MISO

SCP_IRQ

0

126

70

56

7

A6

A5

A0

R/W

MSB

LSB

MSB

LSB

1/