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TMS320VC5509 Datasheet(PDF) 74 Page - Texas Instruments |
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TMS320VC5509 Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 122 page  Electrical Specifications 74 April 2001 − Revised September 2004 SPRS163G 5.3 Electrical Characteristics Over Recommended Operating Case Temperature Range (Unless Otherwise Noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage DN, DP, and PU† DVDD = 3.3 ± 0.3 V, IOH = −300 µA 2.8 3.6 V VOH High-level output voltage All other outputs DVDD = 3.3 ± 0.3 V, IOH = MAX 2.4 V SDA & SCL‡ At 3 mA sink current 0 0.4 VOL Low-level output voltage DN and DP† IOL = 3.0 mA 0.3 V VOL Low-level output voltage All other outputs IOL = MAX 0.4 V IIZ Input current for outputs in Output-only or I/O pins with bus keepers (enabled) DVDD = MAX, VO = VSS to DVDD −500 500 A IIZ Input current for outputs in high-impedance All other output-only or I/O pins DVDD = MAX VO = VSS to DVDD −5 5 µA Input pins with internal pulldown (enabled) DVDD = MAX, VI = VSS to DVDD 30 300 II Input current Input pins with internal pullup (enabled) DVDD = MAX, VI = VSS to DVDD −300 −30 A II Input current X2/CLKIN DVDD = MAX, VI = VSS to DVDD −50 50 µA All other input-only pins DVDD = MAX, VI = VSS to DVDD −5 5 IDDC CVDD Supply current, CPU + internal memory access§ CVDD = 1.6V CPU clock = 144 MHz TC = 25_C 0.90 mA/ MHz IDDP DVDD supply current, pins active¶ DVDD = 3.3 V CPU clock = 144 MHz TC = 25_C 5.5 mA IDDC CVDD supply current, standby# Oscillator disabled. All domains in low-power state CVDD = 1.6V TC = 25_C 250 µA IDDP DVDD supply current, standby Oscillator disabled. All domains in low-power state. DVDD = 3.3 V No I/O activity TC = 25_C 10 µA Ci Input capacitance 3 pF Co Output capacitance 3 pF † USB I/O pins DP and DN can tolerate a short circuit at D+ and D− to 0 V or 5 V, as long as the recommended series resistors (see Figure 5−40) are connected between the D+ and DP (package), and the D− and DN (package). Do not apply a short circuit to the USB I/O pins DP and DN in absence of the series resistors. ‡ The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down. § CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain are active. All other domains are idled. ¶ One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF load. # In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby current will be higher if an external clock source tries to drive the X2/CLKIN pin during this time. NOTE: USB PLL is powered from the core supply and is susceptible to core power supply ripple. The maximum allowable supply ripple is 1% for 1 Hz to 5 kHz; 1.5% for 5 kHz to 10 MHz; 3% for 10 MHz to 100 MHz, and less than 5% for 100 MHz or greater. |
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