TMS320VC5509 datasheet(25/122 Pages) TI

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Introduction

April 2001 − Revised September 2004

SPRS163G

Table 2−3. Signal Descriptions (Continued)

TERMINAL

NAME

RESET

CONDITION

BK‡

FUNCTION

I/O/Z†

MULTIPLEXED

SIGNAL NAME

MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS

CLKR0

I/O/Z

McBSP0 receive clock. CLKR0 serves as the serial shift clock for the serial

port receiver. At reset, this pin is in high-impedance mode.

Hi-Z

DR0

McBSP0 receive data

Input

FSR0

I/O/Z

McBSP0 receive frame synchronization. The FSR0 pulse initiates the data

receive process over DR0. At reset, this pin is in high-impedance mode.

Hi-Z

CLKX0

I/O/Z

McBSP0 transmit clock. CLKX0 serves as the serial shift clock for the

serial port transmitter. The CLKX0 pin is configured as input after reset.

Input

DX0

O/Z

McBSP0 transmit data. DX0 is placed in the high-impedance state when

not transmitting, when RESET is asserted, or when OFF is low.

Hi-Z

FSX0

I/O/Z

McBSP0 transmit frame synchronization. The FSX0 pulse initiates the

data transmit process over DX0. Configured as an input following reset.

Input

S10

I/O/Z

McBSP1

receive

clock

MultiMedia

Card/Secure

Digital1

command/response. At reset, this pin is configured as McBSP1.CLKR.

McBSP1.CLKR

I/Z

McBSP1 receive clock. McBSP1.CLKR serves as the serial shift clock for

the serial port receiver. McBSP1.CLKR is selected when the External Bus

Selection Register has 00 in the Serial Port1 Mode bit field or following

reset.

Input

MMC1.CMD

SD1.CMD

I/O/Z

MMC1 or SD1 command/response is selected when the External Bus

Selection Register has 10 in the Serial Port1 Mode bit field.

S11

I/O/Z

McBSP1 data receive or Secure Digital1 data1. At reset, this pin is

configured as McBSP1.DR.

McBSP1.DR

I/Z

McBSP1 serial data receive. McBSP1.DR is selected when the External

Bus Selection Register has 00 in the Serial Port1 Mode bit field or following

reset.

Input

SD1.DAT1

I/O/Z

SD1 data1 is selected when the External Bus Selection Register has 10 in

the Serial Port1 Mode bit field.

S12

I/O/Z

McBSP1 receive frame synchronization or Secure Digital1 data2. At reset,

this pin is configured as McBSP1.FSR.

McBSP1.FSR

I/Z

McBSP1 receive frame synchronization. The McBSP1.FSR pulse initiates

the data receive process over McBSP1.DR.

Input

SD1.DAT2

I/O/Z

SD1 data2 is selected when the External Bus Selection Register has 10 in

the Serial Port1 Mode bit field.

S13

O/Z

McBSP1 serial data transmit or MultiMedia Card/Secure Digital1 serial

clock. At reset, this pin is configured as McBSP1.DX.

McBSP1.DX

O/Z

McBSP1

serial

data

transmit.

McBSP1.DX

placed

the

high-impedance state when not transmitting, when RESET is asserted, or

when OFF is low. McBSP1.DX is selected when the External Bus

Selection Register has 00 in the Serial Port1 Mode bit field or following

reset.

Hi-Z

MMC1.CLK

SD1.CLK

MMC1 or SD1 serial clock is selected when the External Bus Selection

† I = Input, O = Output, S = Supply, Hi-Z = High-impedance

‡ BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer

TMS320VC5509 Datasheet(PDF) 25 Page - Texas Instruments

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