LP5523 datasheet(18/56 Pages) TI1

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LP5523

SNVS550D – SEPTEMBER 2009 – REVISED MAY 2013

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Control Register Read Cycle

•

Master device generates a start condition.

•

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

•

Slave device sends acknowledge signal if the slave address is correct

•

Master sends control register address (8 bits).

•

Slave sends acknowledge signal.

•

Master device generates repeated start condition.

•

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

•

Slave sends acknowledge signal if the slave address is correct.

•

Slave sends data byte from addressed register.

•

If the master device sends an acknowledge signal, the control register address will be incremented by one.

Slave device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition

Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-

bit word is sent to the LP5523, the internal address index counter will be incremented by one, and the next

increment feature is enabled by writing EN_AUTO_INCR bit high in the MISC register (addr 36h). Note: serial

bus address auto increment is not supported for register addresses from 16 to 1E.

Table 2. Auto Increment Example.

CHIP

REG

MASTER

START

ADDR

WRITE

DATA

STOP

ADDR

=32H

LP5523

ACK

The LP5523 is controlled by a set of registers through the two-wire serial interface port. Some register bits are

reserved for future use. Table 3 below lists device registers, their addresses and their abbreviations. A more

detailed description is given in Control Register Details.

Table 3. Control Register Map

Hex

Read/

Default Value

Bit(s)

Bit Mnemonic and Description

Address

Write

After Reset

CHIP_EN

[6]

R/W

x0xxxxxx

0 = LP5523 not enabled

1 = LP5523 enabled

ENGINE1_EXEC

[5:4]

R/W

xx00xxxx

ENABLE / ENGINE

Engine 1 program execution control

CNTRL1

ENGINE2_EXEC

[3:2]

R/W

xxxx00xx

Engine 2 program execution control

ENGINE3_EXEC

[1:0]

R/W

xxxxxx00

Engine 3 program execution control

ENGINE1_MODE

[5:4]

R/W

xx00xxxx

ENGINE 1 mode control

ENGINE2_MODE

ENGINE CNTRL2

[3:2]

R/W

xxxx00xx

ENGINE 2 mode control

ENGINE3_MODE

[1:0]

R/W

xxxxxx00

ENGINE 3 mode control

OUTPUT

D9_RATIO_EN

DIRECT/RATIOMETRIC

[0]

R/W

xxxxxxx0

Enables ratiometric dimming for D9 output.

MSB

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