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LP5523 Datasheet(PDF) 5 Page - Texas Instruments |
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LP5523 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 56 page ![]() LP5523 www.ti.com SNVS550D – SEPTEMBER 2009 – REVISED MAY 2013 LED Driver Electrical Characteristics (1) (2) (3) Symbol Parameter Condition Min Typ Max Units Leakage Current (outputs D1 ILEAKAGE PWM = 0% 0.1 1 µA to D9) IMAX Maximum Source Current Outputs D1 to D9 25.5 mA −4 +4 IOUT Output Current Accuracy (4) Output current set to 17.5 mA % −5 +5 IMATCH Matching (4) Output current set to 17.5 mA 1 2.5 % fLED LED Switching Frequency 312 Hz VSAT Saturation Voltage (5) Output current set to 17.5 mA 45 100 mV (1) The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. (2) All voltages are with respect to the potential at the GND pin. (3) Min and Max limits are ensured by design, test, or statistical analysis. (4) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current. Matching is the maximum difference from the average. For the constant current outputs on the part (D1 to D9), the following are determined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG). Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) is considered the matching figure. Note that some manufacturers have different definitions in use. (5) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at VOUT – 1V. LED Test Electrical Characteristics (1) (2) (3) Symbol Parameter Condition Min Typ Max Units LSB Least Significant Bit 30 mV EABS Total Unadjusted Error (4) VIN_TEST = 0V to VDD <±3 ±4 LSB tCONV Conversion Time 2.7 ms VIN_TEST DC Voltage Range 0 5 V (1) The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. (2) All voltages are with respect to the potential at the GND pin. (3) Min and Max limits are ensured by design, test, or statistical analysis. (4) Total unadjusted error includes offset, full-scale, and linearity errors. Logic Interface Characteristics (1) (2) (3) Symbol Parameter Condition Min Typ Max Units Logic input EN VIL Input Low Level 0.5 V VIH Input High Level 1.2 V II Input Current −1.0 1.0 µA tDELAY Input Delay (4) 2 µs Logic input SCL, SDA, TRIG, CLK, ASEL0, ASEL1 VIL Input Low Level 0.2xVEN V VIH Input High Level 0.8xVEN V II Input Current −1.0 1.0 µA Logic output SDA, TRIG, INT VOL Output Low Level IOUT = 3 mA (pullup current) 0.3 0.5 V IL Output Leakage Current VOUT = 2.8V 1.0 µA Logic output GPO VOL Output Low Level IOUT = 3 mA 0.3 0.5 V VDD VOH Output High Level IOUT = −2 mA VDD −0.5 −0.3 (1) The Electrical characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured. (2) All voltages are with respect to the potential at the GND pin. (3) Min and Max limits are ensured by design, test, or statistical analysis. (4) The I2C host should allow at least 500 µs before sending data to the LP5523 after the rising edge of the enable line. Copyright © 2009–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LP5523 |
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