GS2965 datasheet(8/41 Pages) SEMTECH

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GS2965 Multi-Rate SDI Reclocker with Equalization &

De-emphasis

Data Sheet

52462 - 4

July 2012

8 of 41

Proprietary & Confidential

1.3 Default Start-up Settings

The GS2965 has some functions that are not accessible via direct pin control, and are

only accessible through the host interface registers. These functions have an internal

pull-up or pull-down resistor that sets the default logic level or start-up state, if it is not

already set by a pin.

If the user wishes to override these logic levels, the associated bit should be programmed

within the PIN_OR_1 register (pin override register) at address 0x0C. The logic values

within the PIN_OR_1 register become active when the user sets the Pin Override Enable

bit to HIGH within that same register.

Table 1-2 shows:

1. The default logic state set by the internal pull up or pull down resistors.

2. The default values within the Pin Override register upon reset.

More details are given in Section 4.15.

Table 1-2: GS2965 Default Start-up Settings

Name

Description

Default State set by

Internal Resistors

Default State within

the Pin Override

DDI_SEL[0:1]

Selects one of two serial digital input signals for

processing. DDI0 is selected by default.

0:0

BYPASS

Bypasses the reclocker stage when set HIGH.

AUTOBYPASS

When set HIGH, this bit automatically bypasses the

reclocker stage when the PLL is not locked to a

supported rate.

AUTO/MAN

When set HIGH, the standard is automatically detected

from the input data rate.

SS0, SS1

When AUTO/MAN is set HIGH, SS[1:0] are outputs

displaying the data rate to which the PLL has locked.

Therefore, they will not have default values.

None

0:0

KBB

Controls the loop bandwidth of the PLL.

Floating

Ground

DATA_MUTE

Mutes the DDO0/DDO0 and DDO1/DDO1 (if data is

selected) outputs when LOW.

DDO1_DISABLE

Disables the DDO1/RCO and DDO1/RCO outputs

when LOW.

DATA/CLOCK

HIGH = DATA

LOW = CLOCK

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