GS2965 datasheet(24/41 Pages) SEMTECH

24 / 41 page

GS2965 Multi-Rate SDI Reclocker with Equalization &

De-emphasis

Data Sheet

52462 - 4

July 2012

24 of 41

Proprietary & Confidential

4.15 Host Interface

4.15.1 Introduction

The GS2965 offers a Serial Peripheral Interface (SPI) to access advanced features and

programmability. The polarity of the HIF pin tells the GS2965 whether or not the host

interface is active (HIF = 0) or in legacy mode (HIF = 1).

Using the host interface, it is possible to override the control pin settings, and such

settings will persist until the device has been powered-down and/or reset. The host

interface is capable of reading hard-wired pin configuration, pin override settings and

the values of all status monitoring pins.

There is an optional 3-state feature available in the Control Status Registers (CSR) that

puts the SPI SDO to high-impedance when it’s not being used (Register: TOP_1, bit: 2).

The maximum operating speed of the SPI is 10MHz.

4.15.2 Legacy Mode & Start-up

In legacy mode, basic configuration of the device (including a subset of equalizer and

de-emphasis settings) are available at the pin level. In this mode, register settings are

automatically set to default so that the GS2965 is live at power-up.

4.15.3 Host Interface Mode & Start-up

In host interface mode, the user gains access to Control and Status Registers (CSRs) that

manage advanced features. In this mode, equalizer and de-emphasis settings are set

through the CSR.

The SPI control port is functional at start-up without the need for a separate, external

reset signal. However, all internal registers must be set to their default state by issuing a

required Reset Command via the SPI.

This is done by setting the R bit (reset) LOW in the command word. This will guarantee

the CSR will not start up in a random state.

A simple way to issue the required reset of the CSR is to hold the slave device’s SDI input

LOW for an entire 64 cycle WRITE communication. Details of the WRITE operation are

found in section 4.15.6 below.

4.15.4 Clock & Data Timing

The SPI signals are Serial Data Input (SDI), Serial Data Output (SDO), active-low Chip

Select (CS), and Serial Clock Input (SCK). The host interface operates in SPI Mode 0, i.e.

DATA

Power down

MUTE

Power down

Table 4-10: Configuration of GS2965 Output Drivers and Mute/Disable Pins

DATA_MUTE

DDO1_DISABLE

DATA/CLOCK

DDO0

DDO1/RCO

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