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GS2965 Datasheet(PDF) 25 Page - Semtech Corporation |
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GS2965 Datasheet(HTML) 25 Page - Semtech Corporation |
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25 / 41 page ![]() GS2965 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52462 - 4 July 2012 25 of 41 Proprietary & Confidential the SDI input will latch data in on the rising edge of SCK. The SDO data output will transition on falling edges of SCK. Data is transmitted or received on the SPI port MSB first LSB last. Figure 4-4: Data Clock Alignment 4.15.5 Single Device Operation For applications with a single device or applications with multiple devices where daisy chaining is not desired, the chain position bits C[6:0] should always be set to 0. As a by-product of the daisy chaining feature, Read and Write operations experience a 32 SCK cycle latency from SDI to SDO. For more details on daisy-chaining, refer to Section 4.15.8 on page 29. Figure 4-5: 16-bit Command Format SCK CS Cycle # 1 2 3 4 5 6 7 8 SDO 1 2 3 4 5 6 7 8 z z 1 2 3 4 5 6 7 8 z z SDI rw A[4:0] R 0 0 Read/ Write Reset Address C N[6:0] = `0000000’ Chain Position |
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