GS2965 datasheet(20/41 Pages) SEMTECH

20 / 41 page

GS2965 Multi-Rate SDI Reclocker with Equalization &

De-emphasis

Data Sheet

52462 - 4

July 2012

20 of 41

Proprietary & Confidential

4.8.1 Lock Detect and Asynchronous Lock

The reference crystal is used to assist the PLL in achieving a short lock time. The lock

detection algorithm is a continuous process, which begins at device power up or after a

system reset, and continues until the device is powered down.

The asynchronous lock time is defined as the time it takes the device to lock when a

video signal is first applied to the serial digital inputs, or when the digital video signal

rate changes.

The synchronous lock time is defined as the time it takes the device to lock to a signal

which has been momentarily interrupted.

4.9 Serial Data Output

The GS2965 features two current-mode differential output drivers, each capable of

driving a maximum of 800mVpp, differential, into an external 100Ω differential load.

Each of the GS2965's output buffers include two on-chip, 50Ω termination resistors.

4.9.1 Output Signal Interface Levels

The serial digital outputs of the GS2965 are compatible when DC-coupled with all

Gennum serial digital interface products that feature a differential LVPECL or CML

receiver designed for SDI applications and operate from 3.3V or 2.5V supplies. This

includes but is not limited to: GS2978, GS2988, and GS2989.

The serial digital data inputs are also compatible when DC-coupled with LVPECL or

CML differential outputs from crosspoint switches which operate from 3.3V or 2.5V

supplies. This includes but is not limited to: GS2974A, GS2974B, and GS2984 equalizers.

4.9.2 Adjustable Output Swing

It is possible, via the host interface, to force the output swing to 400mVpp or 800mVpp

differential, when the outputs are terminated with 50Ω loads.

The default output swing upon power-up is 400mVpp differential.

4.9.3 Output De-emphasis

The GS2965 features adjustable output de-emphasis to compensate for PCB trace

dielectric losses.

The output de-emphasis has eight settings, evenly distributed from a minimum of 0dB

(output de-emphasis OFF) to a peak de-emphasis setting that is optimized for

compensating the high-frequency losses associated with approximately 20 inches of

5-mil stripline in FR4 material. These settings are accessible via the serial host interface.

The action of the de-emphasis settings is to attenuate the trailing edge of the output data

waveform relative to the output swings set through the host interface.

De-emphasis is turned OFF when in Bypass mode.

The default de-emphasis setting upon power-up is 0dB (OFF).

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