TAS5026 datasheet(9/48 Pages) TI

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Introduction

SLES041B—November 2002

TAS5026

1.4

Ordering Information

Texas Instruments

Audio Solutions

5026

PAG

Device Number

Temperature Range

Package Type

AVAILABLE OPTIONS

PACKAGE

PLASTIC 64-PIN TQFP

(PAG)

°C to 70°C

TAS5026CPAG

–40

°C to 85°C

TAS5026IPAG

1.5

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

AVDD_OSC

PWR

Analog power supply for internal oscillator cells

AVDD_PLL

PWR

3.3-V analog power supply for PLL

AVSS_OSC

AOUT

Analog ground for internal oscillator cells

AVSS_PLL

PWR

Analog ground for PLL

CLIP

Digital clipping indicator, active low

CS0

I2C device address select. This is an active high pin.

DBSPD

Sample rate is double speed (88.2 kHz or 96 kHz), active high

DM_SEL1

De-emphasis select bit 1 (0 = none, 01 = 32 kHz, 10 = 44.1 kHz

DM_SEL2

De-emphasis select bit 2, 10 = 48 kHz, 11= undefined (none)

DVDD_PWM

PWR

3.3-V digital power supply for PWM

DVDD_RCL

PWR

3.3-V digital power supply for re-clocker

DVDD

PWR

3.3-V digital power supply for digital core and most of I/O buffers

DVSS

Voltage regulator enable, active low

DVSS_PWM

PWR

Digital ground for PWM

DVSS_RCL

PWR

Digital ground for re-clocker

DVSS1

8, 26,

31, 32

PWR

Digital ground for digital core and most of I/O buffers

ERR_RCVY

Error recovery, active low

LRCLK

I/O

Serial audio data left / right clock (sampling rate clock) (input when M_S = 0; output when M_S

= 1)

M_S

Master/slave mode input signal (master = 1, slave = 0)

MCLK_IN

MCLK input, slave mode

MCLK_OUT

MCLK output buffered system clock output M_S = 1; otherwise set to 0

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