TAS5026 datasheet(10/48 Pages) TI

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Introduction

SLES041B—November 2002

TAS5026

TERMINAL

DESCRIPTION

I/O

NAME

DESCRIPTION

I/O

NO.

MUTE

Mute input signal, active low

1, 7,

27, 49,

No connection

PDN

Power down. This signal is active low.

PLL_FLT_OUT

PLL external filter

PLL_FLT_RET

PLL external filter

PWM_AM_1

PWM 1 output (differential -); {Positive H-bridge side}

PWM_AM_2

PWM 2 output (differential -); {Positive H-bridge side}

PWM_AM_3

PWM 3 output (differential -); {Positive H-bridge side}

PWM_AM_4

PWM 4 output (differential -); {Positive H-bridge side}

PWM_AM_5

PWM 5 output (differential -); {Positive H-bridge side}

PWM_AM_6

PWM 6 output (differential -); {Positive H-bridge side}

PWM_AP_1

PWM 1 output (differential +); {Positive H-bridge side}

PWM_AP_2

PWM 2 output (differential +); {Positive H-bridge side}

PWM_AP_3

PWM 3 output (differential +); {Positive H-bridge side}

PWM_AP_4

PWM 4 output (differential +); {Positive H-bridge side}

PWM_AP_5

PWM 5 output (differential +); {Positive H-bridge side}

PWM_AP_6

PWM 6 output (differential +); {Positive H-bridge side}

RST

System reset input. This signal is an active low.

SCL

I2C clock signal

SCLK

I/O

Serial audio data clock (master mode = output, slave mode = input)

SDA

I/O

I2C data signal

SDIN1

Serial audio data 1 input

SDIN2

Serial audio data 2 input

SDIN3

Serial audio data 3 input

VALID_1

Output indicating validity of PWM outputs, channel 1, active high

VALID_2

Output indicating validity of PWM outputs, channel 2, active high

VALID_3

Output indicating validity of PWM outputs, channel 3, active high

VALID_4

Output indicating validity of PWM outputs, channel 4, active high

VALID_5

Output indicating validity of PWM outputs, channel 5, active high

VALID_6

Output indicating validity of PWM outputs, channel 6, active high

XTL_IN

AIN

Crystal or TTL level clock input

XTL_OUT

AOUT

Crystal output (not for external usage)

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