TAS5026 datasheet(27/48 Pages) TI

27 / 48 page

Architecture Overview

SLES041B—November 2002

TAS5026

Read and write operations to the TAS5026 can be done using single byte or multiple byte data transfers.

2.5.1 Single Byte Write

As shown in Figure 2–14, a single byte data write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction

of the data transfer. For a write data transfer, the read/write bit is 0. After receiving the correct I2C device

address and the read/write bit, the TAS5026 device responds with an acknowledge bit. Next, the master

transmits the address byte or bytes corresponding to the TAS5026 internal memory address being accessed.

After receiving the address byte, the TAS5026 again responds with an acknowledge bit. Next, the master

device transmits the data byte to be written to the memory address being accessed. After receiving the data

byte, the TAS5026 again responds with an acknowledge bit. Finally, the master device transmits a stop

condition to complete the single byte data write transfer.

R/W ACK A7

ACK

Start Condition

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Data Byte

Figure 2–14. Single Byte Write Transfer

2.5.2 Multiple Byte Write

A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes

are transmitted by the master device to TAS5026 as shown in Figure 2–15. After receiving each data byte,

the TAS5026 responds with an acknowledge bit.

D0 ACK

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Last Data Byte

R/W ACK A7

ACK D7

D0 ACK

Start Condition

Acknowledge

First Data Byte

Other

Data Bytes

Figure 2–15. Multiple Byte Write Transfer

2.5.3 Single Byte Read

As shown in Figure 2–16, a single byte data read transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. For the data read transfer, a write followed

by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory

address to be read. As a result, the read/write bit is 0. After receiving the TAS5026 address and the read/write

bit, the TAS5026 responds with an acknowledge bit. Also, after sending the internal memory address byte or

bytes, the master device transmits another start condition followed by the TAS5026 address and the read/write

bit again. This time the read/write bit is a 1 indicating a read transfer. After receiving the TAS5026 and the

read/write bit, the TAS5026 again responds with an acknowledge bit. Next, the TAS5026 transmits the data

byte from the memory address being read. After receiving the data byte, the master device transmits a not

acknowledge followed by a stop condition to complete the single byte data read transfer.

A0 R/W ACK A7

A0 ACK

ACK

Start

Condition

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Data Byte

D0 ACK

I2C Device Address and

Read/Write Bit

Repeat Start Condition

Not

Acknowledge

R/W

Figure 2–16. Single Byte Read

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