MIC7401 datasheet(29/68 Pages) MICREL

29 / 68 page

Micrel, Inc.

MIC7401

March 16, 2015

Revision 1.0

During start-up sequencing if Output 1 is still shorted,

Outputs 2 through 4 will come up normally. Once an

overcurrent condition is sensed, then the fault register is

set to “1” and the start-up sequence will stop and no

further outputs will be enabled. See Figure 9 for default

start-up sequence.

Boost Current Limit

The boost current limit features cycle-by-cycle protection.

The duty cycle is cut immediately once the current limit is

hit. When the boost current limit is hit for five consecutive

cycles, the FAULT signal is asserted and remains

asserted with the boost converter keeping on running

until the boost is powered off.

This protects the boost in normal overload conditions, but

not in a short-to-ground case. For a short circuit to

ground, the boost current limit will not be able to limit the

inductor current. This short-circuit condition is sensed by

the current in the disconnect switch. When the disconnect

switch current limit is hit for four consecutive master clock

cycles (2MHz), regardless if the boost is switching or not,

both the disconnect switch and boost are latched off

automatically and the FAULT signal is asserted.

The output can be turned back on by recycling the input

power or by software control. To clear the overcurrent

fault by software control, set the enable register bit to “0”

then clear the overcurrent fault by setting the fault

Global Power Good Pin

The global power-good output indicates that all the

outputs are above the 91% limit after the power-up

sequence is completed. Once the power-up sequence is

complete, the global power good output stays high unless

an output falls below its power-good limit, a thermal fault

occurs, the input voltage drops below the lower UVLO

threshold or an output is turned OFF by setting the

enable register bit to “0” unless the PGOOD_MASK[x] bit

is set to “1” (Default).

A power-good mask bit can be used to control the global

power good output. The power-good mask feature is

programmed through the PGOOD_MASK[x] registers and

is used to ignore an individual power-good fault.

When

masked, PGOOD_MASK[x] bit is set to “1”, an individual

power good fault will not cause the global power good

output to de-assert.

If all the PGOOD_MASK[x] bit are set to “1”, then the

power good output de-asserts as soon as the first output

starts to rise. The PGOOD_MASK[x] bit of the last output

must be set to “0” to have the PG output stay low until the

last output reaches 91% of its final value.

The global power-good output is an open-drain output. A

pull-up resistor can be connected to VIN or VOUT. Do not

connect the pull-up resistor to a voltage higher than AVIN.

Standard Delay

There is a programmable timer that is used to set the

standard delay time between each time slot. The timer

starts as soon as the previous time slot’s output power

good

goes high. When the delay completes,

the

regulators assigned to that time slot are enabled, see

Figure 8.

Figure 8. Standard Delay Time

Power-Up Sequencing

When power is first applied to the MIC7401, all I²C

registers are loaded with their default values from the

EEPROM. There is about a 1.5ms delay before the first

regulator is enabled while the MIC7401 goes through the

initialization process. The DELAY register’s STDEL bits

set the delay between powering up each regulator at

initial power up.

The sequencing registers allow the outputs to come up in

any order. There are six time slots that an output can be

configured to power up in.

Each time slot can be

programmed for up to six regulators to be turned on at

once or none at all.

Figure 9 shows an example of this feature. VOUT4 is

enabled in time slot 1. After a 1ms delay, VOUT2 and VOUT3

are enable at the same time in time slot 2. The 1ms is the

standard delay for all of the outputs and can be

programmed from 0ms to 7ms in 1ms. Next, VOUT1 is

powered up in time slot 3 and VOUT5 in time slot 4. There

are no regulators programmed for time slot 5. Finally,

VOUT6 is powered up in time slot 6. The global power good

output, VPG, goes high as soon as the last output reaches

91% of its final value. Here the PGOOD_MASK[6] bit is

set to “0”.

MIC7401 Datasheet(PDF) 29 Page - Micrel Semiconductor

MIC7401 Datasheet(HTML) 29 Page - Micrel Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL