DS2155 datasheet(62/262 Pages) DALLAS

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DS2156

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Table 9-A. E1 Sync/Resync Criteria

FRAME OR

MULTIFRAME

LEVEL

SYNC CRITERIA

RESYNC CRITERIA

ITU SPEC.

FAS

FAS present in frame N and

N + 2; FAS not present in

frame N + 1

Three consecutive incorrect

FAS received

Alternate: (E1RCR1.2 = 1) The

above criteria is met or three

consecutive incorrect bit 2 of

non-FAS received

G.706

4.1.1

4.1.2

CRC4

Two valid MF alignment

words found within 8ms

915 or more CRC4 codewords

out of 1000 received in error

G.706

4.2 and 4.3.2

CAS

Valid MF alignment word

found and previous time slot

16 contains code other than

all 0s

Two consecutive MF

alignment words received in

error

G.732

5.2

E1RCR2

E1 Receive Control Register 2

34h

Bit #

Name

Sa8S

Sa7S

Sa6S

Sa5S

Sa4S

—

RCLA

Default

Bit 0/Receive Carrier-Loss (RCL) Alternate Criteria (RCLA). Defines the criteria for a receive carrier-loss

condition for both the framer and LIU.

0 = RCL declared upon 255 consecutive 0s (125µs)

1 = RCL declared upon 2048 consecutive 0s (1ms)

Bits 1, 2/Unused, must be set to 0 for proper operation

Bit 3/Sa4 Bit Select (Sa4S). Set to 1 to have RLCLK pulse at the Sa4 bit position; set to 0 to force RLCLK low

during Sa4 bit position. See Section 34 for details.

Bit 4/Sa5 Bit Select (Sa5S). Set to 1 to have RLCLK pulse at the Sa5 bit position; set to 0 to force RLCLK low

during Sa5 bit position. See Section 34 for details.

Bit 5/Sa6 Bit Select (Sa6S). Set to 1 to have RLCLK pulse at the Sa6 bit position; set to 0 to force RLCLK low

during Sa6 bit position. See Section 34 for details.

Bit 6/Sa7 Bit Select (Sa7S). Set to 1 to have RLCLK pulse at the Sa7 bit position; set to 0 to force RLCLK low

during Sa7 bit position. See Section 34 for details.

Bit 7/Sa8 Bit Select (Sa8S). Set to 1 to have RLCLK pulse at the Sa8 bit position; set to 0 to force RLCLK low

during Sa8 bit position. See Section 34 for details.

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