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DS2155 Datasheet(PDF) 50 Page - Dallas Semiconductor |
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DS2155 Datasheet(HTML) 50 Page - Dallas Semiconductor |
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50 / 262 page  DS2156 50 of 262 condition. For example, SR2 has a bit that is set when the device goes into a loss-of-sync state (SR2.0, a condition bit) and a bit that is set (SR2.4, an event bit) when the loss-of-sync condition clears (goes in sync). Some of the status register bits (condition bits) do not have a separate bit for the “condition clear” event but rather the status bit can produce interrupts on both edges, setting and clearing. These bits are marked as double interrupt bits. An interrupt is produced when the condition occurs and when it clears. 6.4 Information Registers Information registers operate the same as status registers except they cannot cause interrupts. They are all latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read-only register. It reports the status of the E1 synchronizer in real time. INFO7 and some of the bits in INFO6 and INFO5 are not latched and it is not necessary to precede a read of these bits with a write. 6.5 Interrupt Information Registers The interrupt information registers provide an indication of which status registers (SR1 through SR9) are generating an interrupt. When an interrupt occurs, the host can read IIR1 and IIR2 to quickly identify which of the nine status registers are causing the interrupt. Register Name: IIR1 Register Description: Interrupt Information Register 1 Register Address: 14h Bit # 7 6 5 4 3 2 1 0 Name SR8 SR7 SR6 SR5 SR4 SR3 SR2 SR1 Default 0 0 0 0 0 0 0 0 Register Name: IIR2 Register Description: Interrupt Information Register 2 Register Address: 15h Bit # 7 6 5 4 3 2 1 0 Name — — — — — — U_RSR SR9 Default 0 0 0 0 0 0 0 0 |
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