DS2155 datasheet(69/262 Pages) DALLAS

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DS2156

69 of 262

IDR

Device Identification Register

0Fh

Bit #

Name

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

Default

Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of

the chip. IDO is the LSB of a decimal code that represents the chip revision.

Bits 4 to 7/Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the DS2156 ID.

10.1 T1/E1 Status Registers

SR2

Status Register 2

18h

Bit #

Name

RYELC

RUA1C

FRCLC

RLOSC

RYEL

RUA1

FRCL

RLOS

Default

Bit 0/Receive Loss-of-Sync Condition (RLOS). Set when the DS2156 is not synchronized to the received data

stream.

Bit 1/Framer Receive Carrier-Loss Condition (FRCL). Set when 255 (or 2048 if E1RCR2.0 = 1) E1 mode or

192 T1 mode consecutive 0s have been detected at RPOSI and RNEGI.

Bit 2/Receive Unframed All-Ones (T1 Blue Alarm, E1 AIS) Condition (RUA1). Set when an unframed all 1s

code is received at RPOSI and RNEGI.

Bit 3/Receive Yellow Alarm Condition (RYEL) (T1 Only). Set when a Yellow Alarm is received at RPOSI and

RNEGI.

Bit 4/Receive Loss-of-Sync Clear Event (RLOSC). Set when the framer achieves synchronization; remains set

until read.

Bit 5/Framer Receive Carrier-Loss Clear Event (FRCLC). Set when the carrier loss condition at RPOSI and

RNEGI is no longer detected.

Bit 6/Receive Unframed All-Ones Clear Event (RUA1C). Set when the unframed all 1s condition is no longer

detected.

Bit 7/Receive Yellow Alarm Clear Event (RYELC) (T1 Only). Set when the receive Yellow Alarm condition is

no longer detected.

DS2155 Datasheet(PDF) 69 Page - Dallas Semiconductor

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