DS2155 datasheet(66/262 Pages) DALLAS

66 / 262 page

DS2156

66 of 262

9.3

E1 Information Registers

INFO3

Information Register 3

12h

Bit #

Name

—

CRCRC

FASRC

CASRC

Default

Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are

received in error.

Bit 1/FAS Resync Criteria Met Event (FASRC). Set when three consecutive FAS words are received in error.

Bit 2/CRC Resync Criteria Met Event (CRCRC). Set when 915/1000 codewords are received in error.

INFO7

Information Register 7 (Real-Time, Non-Latched Register)

30h

Bit #

Name

CSC5

CSC4

CSC3

CSC2

CSC0

FASSA

CASSA CRC4SA

Default

Bit 0/CRC4 MF Sync Active (CRC4SA). Set while the synchronizer is searching for the CRC4 MF alignment

word. This is a read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write.

Bit 1/CAS MF Sync Active (CASSA). Set while the synchronizer is searching for the CAS MF alignment word.

This is a read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write.

Bit 2/FAS Sync Active (FASSA). Set while the synchronizer is searching for alignment at the FAS level. This is a

read-only, non-latched, real-time bit. It is not necessary to precede the read of this bit with a write.

Bits 3 to 7/CRC4 Sync Counter Bits (CSC0, CSC2 to CSC4). The CRC4 sync counter increments each time the

8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained

synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (E1RCR1.3 = 0).

This counter is useful for determining the amount of time the framer has been searching for synchronization at the

CRC4 level. ITU G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400ms, then

the search should be abandoned and proper action taken. The CRC4 sync counter rolls over. CSC0 is the LSB of

the 6-bit counter. (Note: The bit next to LSB is not accessible. CSC1 is omitted to allow resolution to >400ms

using 5 bits.) These are read-only, non-latched, real-time bits. It is not necessary to precede the read of these bits

with a write.

DS2155 Datasheet(PDF) 66 Page - Dallas Semiconductor

DS2155 Datasheet(HTML) 66 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL