TDP158 datasheet(26/55 Pages) TI1

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TDP158

SLLSEX2 – DECEMBER 2016

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Table 3. Receiver EQ Programming and Values (continued)

Global

Independent Lane Control

RX EQ

(dB)

Pin Control (1)

I2C Control

I2C Control (2)

{EQ2,EQ1}

P0_Reg0D[6:3]

P0_Reg4E[3:0]

P0_Reg4E[7:4]

P0_Reg4F[3:0]

CLK(2)(3)

P0_Reg4F[7:4]

4’b1010

4’b1011

4’b1100

14.5

2’b1Z

4’b1101

4’b1110

15.5

2’b11

4’b1111

8.3.7 Input Signal Detect Block

When SIG_EN is enabled through I2C the receiver looks for a valid HDMI clock signal input and is fully functional

when a valid signal is detected. If no valid HDMI clock signal is detected, the device enters standby mode waiting

for a valid signal at the clock input. All of the TMDS outputs and IN_D[0:2] are in high-Z status. HDMI signal

detect circuit is default enabled. If there is a loss of signal reg20h[5] can be read to determine if the TDP158 has

not detected a valid signal or not.

8.3.8 Transmitter Impedance Control

HDMI2.0 standard requires a source termination impedance in the 75

Ω to 150Ω range for data rates > 3.4Gbps.

HDMI1.4b requires no source termination but has a provision for using 150

Ω to 300 Ω for higher data rates. The

TDP158 has three termination levels that are selectable using pin 16 when programming through pin strapping or

when using I2C programming through reg0Bh[4:3]. When the TMDS_CLOCK_RATIO_STATUS bit, reg0Bh[1] = 1

theTDP158 automatically turns on the 75

Ω to 150 Ω source termination otherwise the termination must be

selected. See Table 4.

Table 4. Source Termination Control Table

Pin 16

Reg0Bh[4:3]

Source Termination

TERM = L

150 Ω ~ 300 Ω

TERM = NC

None

Automatic set based upon TMDS_CLOCK_RATIO_STATUS bit

TERM = H

75 Ω ~ 150 Ω

NOTE

If the TMDS_CLOCK_RATIO_STATUS bit = 1, the TDP158 automatically switches in 75

Ω ~ 150 Ω termination.

TDP158 Datasheet(PDF) 26 Page - Texas Instruments

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