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TDP158 Datasheet(PDF) 9 Page - Texas Instruments |
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TDP158 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 55 page  9 TDP158 www.ti.com SLLSEX2 – DECEMBER 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) The Typical rating is simulated at 3.3 V VCC and 1.1 V VDD and at 27°C temperature unless otherwise noted (2) The Maximum rating is simulated at 3.6 V VCC and 1.27 V VDD and at 85°C temperature unless otherwise noted 6.7 Electrical Characteristics, TMDS Differential Output over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX(2) UNIT VOH Single-ended high level output voltage Data rate ≤ 1.65 Gbps SDA_CTL/PRE = L; TERML = NC; OE = H; DR = 750 Mbps VCC - 10 VCC + 10 V Single-ended high level output voltage Datarate >1.65 Gbps and < 3.4 Gbps SDA_CTL/PRE = L ; TERM = L, NC; OE = H; DR = 2.97 Gbps VCC - 200 VCC + 10 V Single-ended high level output voltage Datarate > 3.4 Gbps and < 6 Gbps SDA_CTL/PRE =L ; TERM = H; OE = H; DR = 6 Gbps VCC - 400 VCC + 10 V VOL Single-ended low level output voltage Data rate ≤1.65 Gbps SDA_CTL/PRE = L ; TERM = NC; OE = H; DR = 750 Mbps VCC - 600 VCC - 400 V Single-ended low level output voltage Datarate >1.65Gbps and <3.4Gbps SDA_CTL/PRE = L ; TERM = L NC; OE = H; DR = 2.97 Gbps VCC - 700 VCC - 400 V Single-ended low level output voltage Datarate > 3.4 Gbps and < 6 Gbps SDA_CTL/PRE = L ; TERM = H; OE = H; DR = 6 Gbps VCC - 1000 VCC - 400 V V(SWING_DA) Single-ended output voltage swing on data lane SDA_CTL/PRE = L ; TERM = H/Z/L; OE = H; DR = 750 Mbs, 2.97 Gbps, 6 Gbps VSADJ = 5.5 kΩ; 400 500 600 mV V(SWING_CLK) Single-ended output voltage swing on clock lane SDA_CTL/PRE = L ; TERM = L, NC; OE = H; Data rate ≤ 3.4 Gbps 400 500 600 mV SDA_CTL/PRE = L ; TERM = H; OE = H; Data rate > 3.4 Gbps 200 300 400 mV ΔV(SWING) Change in single-end output voltage swing per 100 Ω ΔVSADJ 20 mV ΔVOCM(SS) Change in steady state output common mode voltage between logic levels -5 5 mV VOD(PP) Output differential voltage before Pre- emphasis; See Pre-emphasis VSADJ = 6 kΩ; SDA_CTL/PRE = H: See Figure 9 600 1000 mV VOD(SS) Steady state output differential voltage See Pre-emphasis VSADJ = 6 kΩ; SDA_CTL/PRE = H, See Figure 9 350 720 mV VSADJ = 5.5 kΩ; SDA_CTL/PRE = L, See Figure 8 350 1000 mV VOD(range) Total TMDS data lanes output differential voltage for HDMI2.0 See Figure 11 3.4 Gbps < Rbit ≤ 3.712 Gps SLEW = H; TERM = H; SDA_CTL/PRE = L; OE = H 335 mV 3.712 Gbps < Rbit < 5.94 Gbp SLEW = H; TERM = H; SDA_CTL/PRE = L; OE = H -19.66 x (RBIT2) + (106.74 x Rbit) + 209.58 mV 5.94 Gbps ≤ Rbit ≤ 6 Gbps SLEW = H; TERM = H; SDA_CTL/PRE = L; OE = H 150 mV IOS Short circuit current limit Main link output shorted to GND 50 mA R(TERM) Source Termination resistance for HDMI2.0 75 150 Ω |
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