TDP158 datasheet(29/55 Pages) TI1

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TDP158

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SLLSEX2 – DECEMBER 2016

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Table 7. Swing and Pre-emphasis Programming Based Upon 6 kΩ VSADJ Resistor

Global Control

Independent Lane Control

Mode

Reg09h[6]

Lane CTL

Reg09[5]

Mode CTL

P0_Reg0C[7:0]

Reg09h[6]

Lane CTL

Reg09[5]

Mode CTL

P0_Reg0C[7:0]

HDMI

8’h00

DP SWG0, PRE0

8’h80

DP SWG0, PRE1

8’hC1

DP SWG0, PRE2

8’h42

DP SWG1, PRE0

8’hC0

8’hA0

DP SWG1, PRE1

8’hF1

8’h21

DP SWG1, PRE2

8’h52

8’h62

DP SWG2, PRE0

8’h20

8’h00

DP SWG2, PRE1

8’h51

8’h61

8.3.12 DP-Mode Description

The TDP158 has the ability to perform as a DisplayPort redriver under the right conditions. The TDP158 is put

into this mode by setting reg09h[5] to 1. The device is now programmable through I2C only. As the transmitter is

a DC coupled transmitter supporting TMDS some external circuits are required to level shift the signal to an AC

coupled DisplayPort signal, see Figure 49. Note that the AUX lines bypass the TDP158. To set the device up

correctly during link training the TDP158 must be programmed using I2C. When this bit is set, the TDP158 does

the following:

•

Ignore SWAP function

•

Ignore SIG_EN function

•

Enable all four lanes and set to support 5.4 Gbps data rate

•

Sets VOD swing to the lowest level based on a 6 kΩ VSADJ resistor value

•

Sets Pre-emphasis to 0 dB

•

Defaults to global lane control

•

Can be set to independent lane control by setting P0_Reg09[6] to a 1. This should be done after

implementing DP Mode. Individual Lane control starts on P0_Reg30 through P0_Reg34 and also P0_Reg4E

and 4F

In order for the system implementer to configure the TDP158 output to the properly requested levels during link

training, the following registers are used.

•

Reg0Ch[7:5] is a global VOD swing control for all four lanes, see Table 7

•

Reg0Ch[1:0] is a global Pre-emphasis control for all four lanes, see Table 7. This register works with

Reg30h[7:6]

•

Reg0D[6:3] is a global EQ control for all four lanes

•

Reg30h[7:6] is to let the TDP158 know what the data rate is. This is used for the delay component for Pre-

emphasis signal.

•

Reg30h[5:2] is used to turn on or off individual lanes

Power down states while in DP-Mode are implemented the same as if in normal operation. See the Electrical

Characteristics, TMDS Differential Output for the outputs based upon the VSADJ 6 kΩ VSADJ resistor.

8.4 Device Functional Modes

8.4.1 DDC Training for HDMI2.0 Data Rate Monitor

As part of discovery the source reads the sink E-EDID information to understand the sink’s capabilities. Part of

this read is HDMI Forum Vendor Specific Data Block (HF-VSDB) MAX_TMDS_Character_Rate byte to determine

the data rate supported. Depending upon the value the source will write to slave address 0xA8 offset 0x20 bit1,

TMDS_CLOCK_RATIO_STATUS. The TDP158 snoops the DDC link to determine the TMDS clock ratio status

and thus sets its own TMDS_CLOCK_RATIO_STATUS bit accordingly. If a ‘1’ is written by the source the TMDS

clock is 1/40 of TMDS bit period. If a ‘0’ is written, then the TMDS clock is 1/10 of TMDS bit period.

TDP158 Datasheet(PDF) 29 Page - Texas Instruments

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