TDP158 datasheet(5/55 Pages) TI1

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TDP158

www.ti.com

SLLSEX2 – DECEMBER 2016

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(1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values, except differential voltages, are with respect to network ground terminal.

(3)

Tested in accordance with JEDEC Standard 22, Test Method A114-B

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2)

MIN

MAX

UNIT

Supply Voltage Range(3)

VCC

–0.3

VDD

–0.3

1.4

Voltage Range

Main Link Input Differential Voltage (IN_Dx)

–0.3

1.56

Main Link Input Single Ended on Pin

–0.3

1.4

TMDS Output ( OUT_Dx)

–0.3

HPD_SRC, VSADJ, SDA_CTL/PRE, OE,

A1/EQ2, A0/EQ1, TERM, I2C_EN, SLEW,

SCL_CTL/SWAP, SDA_SRC, SCL_SRC

–0.3

HDP_SNK, SDA_SNK, SCL_SNK

–0.3

Continuous power dissipation

See Thermal Information

Storage temperature, Tstg

–65

150

°C

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2)

JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings

VALUE

UNIT

V(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)

±2000

Charged-device model (CDM), per JEDEC specification JESD22-

C101(2)

±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

VCC

Supply Voltage Nominal Value 3.3 V

3.6

VDD

Supply Voltage Nominal Value 1.1 V

1.27

Junction temperature

–40

105

°C

Operating free-air temperature (TDP158)

°C

Operating free-air temperature (TDP158I)

–40

°C

MAIN LINK DIFFERENTIAL PINS

VID(EYE)

Peak-to-peak input differential voltage See Figure 19

1200

VID(DC)

The input differential voltage Peak-to peak DC level, See Figure 19

200

1200

VIC

Input Common Mode Voltage (Internally Biased)

0.5

0.9

Data rate

0.25

Gbps

VSADJ

TMDS compliant swing voltage bias resistor Nominal 6 k

Ω

–1%

DDC, I2C, HPD, AND CONTROL PINS

VI(DC)

DC Input Voltage

HDP_SNK, SDA_SNK, SCL_SNK,

–0.3

5.5

SDA_SRC, SCL_SRC; All other Local I2C, and

control pins

–0.3

3.6

VIL

Low-level input voltage at DDC

0.3 x VCC

Low-level input voltage at HPD

0.8

Low-level input voltage at SDA_CTL/PRE, OE, A1/EQ2, A0/EQ1, TERM,

I2C_EN, SLEW, SCL_CTL/SWAP pins only

0.3

VIM

Mid-Level input voltage at A1/EQ2, A0/EQ1, TERM, SLEW pins only

1.2

1.6

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