TDP158 datasheet(30/55 Pages) TI1

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TDP158

SLLSEX2 – DECEMBER 2016

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Device Functional Modes (continued)

The TDP158 will always default to 1/10 of TMDS bit period unless a ‘1’ is written to address 0xA8 offset 0x20 bit

1 or during a read by the source this bit is set. This helps determine source termination when automatic source

termination select is enabled. Otherwise this bit has no other impact on the TDP158. When HPD_SNK is de-

asserted this bit is reset to default values of 0 if this feature is enabled. If the source does not write this bit to the

sink or during the read the bit is not set the TDP158 will not set the output termination to 75

Ω to 150 Ω in

support of HDMI2.0. If the TDP158 has entered a power down state using HDP_SNK = low or OE = low this bit is

cleared and will be set on a read or write where this bit is set. When DDC_TRAIN_SETDISABLE is 1’b0 the

TMDS_CLOCK_RATIO_STATUS bit will reflect the value of the DDC snoop. When DDC_TRAIN_SETDISABLE

is 1’b1 the TMDS_CLOCK_RATIO_STATUS bit is set by I2C and DDC snoop is ignored and thus automatic

TERM control is ignored and must be manually set. To go back to snoop and automatic TERM control the

DDC_TRAIN_SETDISABLE bit has to be cleared and TERM set back to automatic control.

8.4.2 DDC Functional Description

The TDP158 solves sink/source level issues by implementing a master/salve control mode for the DDC bus.

When the TDP158 detects the start condition on the DDC bus from the SDA_SRC/SCL_SRC it transfers the data

or clock signal to the SDA_SNK/SCL_SNK with little propagation delay. When SDA_SNK detects the feedback

from the downstream device the TDP158 pulls up or pull down the SDA_SRC bus and deliver the signal to the

source.

The DDC link defaults to 100kbps but can be set to various values including 400 kbps by setting the correct

value to address 22h through the I2C interface. The HPD goes to high impedance when VCC is under low power

conditions, < 1.5 V.

NOTE

The TDP158 uses clock stretching for DDC transactions. As there are sources and sinks

that do not perform this function correctly a system may not work correctly as DDC

transactions are incorrectly transmitted/received. To overcome this, a snoop configuration

can be implemented where the SDA/SCL from the source is connected directly to the

SDA/SCL pins. The TDP158 needs the SDA_SNK and SCL_SNK pins connected to the

sink DDC pins so that the TMDS_CLOCK_RATIO_STATUS bit can be automatically set

otherwise it will have to be set through I2C. For best noise immunity, the SDA_SRC and

SCL_SRC pins should be connected to GND. Care must be taken when this configuration

is being implemented as the voltage level for DDC between the source and sink may be

different, 3.3 V vs 5 V.

8.5 Register Maps

The TDP158 local I2C interface is enabled when I2C_EN is high. The SCL_CTL and SDA_CTL terminals are

used for I2C clock and data respectively. The TDP158 I2C interface conforms to the two-wire serial interface

defined by the I2C Bus Specification, Version 2.1 (January 2000), and supports the fast mode transfer up to 400

kbps. The device address byte is the first byte received following the START condition from the master device.

The 7 bit device address for TDP158 decides by the combination of A0/EQ1 and A1/EQ2. Table 8 clarifies the

TDP158 target address.

Table 8. TDP158 I2C Device Address Description

A1/A0

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (W/R)

HEX

0/1

BC/BD

0/1

BA/BB

0/1

B8/B9

0/1

B6/B7

The local I2C is 5-V tolerant, and no additional circuitry required. Local I2C buses run at 400 kHz supporting fast-

mode I2C operation.

TDP158 Datasheet(PDF) 30 Page - Texas Instruments

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