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TDP158 Datasheet(PDF) 35 Page - Texas Instruments |
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TDP158 Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 55 page ![]() 35 TDP158 www.ti.com SLLSEX2 – DECEMBER 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8.5.8 CSR BIT FIELD DEFINITIONS – MISC CONTROL 0Ch (address = 0Ch) Figure 32. MISC CONTROL 0Ch Field Descriptions 7 6 5 4 3 2 1 0 VSWING_DATA VSWING_CLK HDMI_TWPST1[1:0] R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 15. MISC CONTROL 0Ch Bit Field Type Reset Description 7:5 VSWING_DATA R/W 3’b000 Data Output Swing Control 000 – Vsadj set (default) 001 – Increase by 7% 010 – Increase by 14% 011 – Increase by 21% 100 – Decrease by 30% 101 – Decrease by 21% 110 – Decrease by 14% 111 – Decrease by 7% 4:2 VSWING_CLK R/W 3’b000 Clock Output Swing Control: Default is set by Vsadj resistor value and the value of reg0Dh[0]. 000 – Vsadj set (default) 001 – Increase by 7% 010 – Increase by 14% 011 – Increase by 21% 100 – Decrease by 30% 101 – Decrease by 21% 110 – Decrease by 14% 111 – Decrease by 7% 1:0 HDMI_TWPST1[1:0] R/W 2’b00 HDMI Pre-emphasis 00 – No Pre-emphasis (default) 01 – 3.5 dB 10 – 6 dB 11 – Reserved NOTE: See Pre-emphasis Section for 6 dB explanation during normal operation supporting HDMI. 8.5.9 CSR BIT FIELD DIFINITIONS, Equalization Control Register (address = 0Dh) Figure 33. Equalization Control Register 7 6 5 4 3 2 1 0 Reserved Data Lane Fixed EQ Values Clock EQ Values DIS_HDMI2_S WG R R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 16. Equalization Control Register Field Descriptions Bit Field Type Reset Description 7 Reserved R 1’b0 Reserved 6:3 Data Lane Fixed EQ Values R/W 4’b0000 (Section Receiver Equalizer and Table 3 for values) 0000 – 0 dB (default) 2:1 Clock EQ Values R/W 2’b00 00 – 0dB (default) 01 – 1.5dB 10 – 3dB 11 – 4.5dB 0 DIS_HDMI2_SWG R/W 1’b0 Disables halving the clock output swing when entering HDMI2.0 mode from TMDS_CLOCK_RATIO_STATUS. 0 – Disables TMDS_CLOCK_RATIO_STATUS control of the clock VOD so output swing is at full swing (default) 1 – Clock VOD is half of set values when TMDS_CLOCK_RATIO_STATUS states in HDMI2.0 mode |
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