TDP158 datasheet(47/55 Pages) TI1

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TDP158

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SLLSEX2 – DECEMBER 2016

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10 Power Supply Recommendations

10.1 Power Management

To minimize the power consumption of customer application, TDP158 used the dual power supply. VCC is 3.3 V

with 10% range to support the I/O voltage. The VDD is 1.1 V with ~ 5% range to supply the internal digital control

circuit. TDP158 operates in 3 different working states.

•

Power down Mode:

–

OE = Low puts the device into its lowest power state by shutting down all function blocks.

–

When OE is re-asserted the transitions from L

→H creates a reset and if the device is programmed

through I2C it must be reprogrammed.

–

Writing a 1 to register 09h[3].

–

OE = High, HPD_SNK = Low for > 2ms

•

Standby Mode:

–

HPD_SNK = High but no valid clock signal detect on clock lane.

•

Normal operation:

–

When HPD assert, the device output will enable based on the signal detector circuit result.

–

HPD_SRC = HPD_SNK in all conditions. The HPD channel operational when VCC over 3 V.

NOTE

When the TDP158 is put into a power down state the I2C registers are cleared. This is

important as the TMDS_CLOCK_RATIO_STATUS bit will be cleared. If cleared and

HDMI2.0 resolutions are to be supported the TDP158 expects the source to write a 1 to

this bit location. If the read has the bit set, the TDP158 will set this bit; otherwise, the

source termination must be set manually.

10.2 Standby Power

The TDP158/I implement a two stage standby power process.

Stage 1: If there is no signal on the Clock line, the max IVCC ~ 5 ma and max IVDD ~ 6 ma.

Stage 2: If a signal is on the clock line like noise or a clock signal, the TDP158 investigates for 3 µs to 5 µs at

which time, it determines if a is clock present.

•

If a clock is detected the TDP158 will go into normal operation.

•

If it is determined that no clock is present the TDP158 will re-enter stage 1.

In stage 2; max IVCC ~ 5 ma and max IVDD ~ 27 ma.

Table 30. Power Modes

INPUTS

STATUS

HPD_SNK

Reg09[2]

IN_CLK

HPD_SRC

IN_Dx

SDA/SCL_CTL

OUT_Dx

OUT_CLK

DDC

Mode

High-Z

Disable

High-Z

Disabled

Power Down

Mode

HPD_SNK

RX Active

Active

TX Active

Active

Normal

operation

No Valid TMDS

Clock

HPD_SNK

D0-D2 Disabled

IN_CLK Active

Active

High-Z

Active

Standby Mode

(Squelch

waiting)

Valid TMDS

Clock

HPD_SNK

RX Active

Active

TX Active

Active

Normal

operation

No Valid TMDS

Clock

HPD_SNK

D0-D2 Disabled

IN_CLK Active

Active

High-Z

Active

Standby Mode

(Squelch

waiting)

Valid TMDS

Clock

HPD_SNK

RX Active

Active

TX Active

Active

Normal

operation

TDP158 Datasheet(PDF) 47 Page - Texas Instruments

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