TDP158 datasheet(33/55 Pages) TI1

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TDP158

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SLLSEX2 – DECEMBER 2016

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Table 12. MISC CONTROL 09h (continued)

Bit

Field

Type

Reset

Description

SIG_EN

R/W

1’b1

This field enable the clock lane activity detect circuitry. See Input

Signal Detect Block

0 – Disable Clock detector circuit closed and receiver always

works in normal operation.

1 – Enable (default) , Clock detector circuit will make receiver

automatic enter the standby state when no valid data detect.

PD_EN

R/W

1’b0

0 – Normal working (default)

1 – Forced Power down by I2C, Lowest Power state

HPD_AUTO_PWRDWN_DISABL

R/W

1’b0

0 – Automatically enters power down mode based on HPD_SNK

(default)

1 – Will not automatically enter power down mode

1:0

I2C_DR_CTL

R/W

2’b10

I2C data rate supported for configuring device.

00 – 5Kbps

01 – 10Kbps

10 – 100Kbps( Default )

11 – 400Kbps

8.5.6 CSR BIT FIELD DEFINITIONS – MISC CONTROL 0Ah (address = 0Ah)

Figure 30. MISC CONTROL 0Ah Field Descriptions

Reserved

HPDSNK_GAT

E_EN

Reserved

SLEW_CTL_DATA

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. MISC CONTROL 0Ah

Bit

Field

Type

Reset

Description

Reserved

1’b0

Reserved

HPDSNK_GATE_EN

R/W

1’b0

The field set the HPD_SNK signal pass through to HPD_SRC or

not and HPD_SRC whether held in the de-asserted state.

0 – HPD_SNK passed through to the HPD_SRC (default)

1 – HPD_SNK will not pass through to the HPD_SRC.

5:2

Reserved

1’b0

Reserved

1:0

SLEW_CTL_DATA

R/W

1’b0

See Slew Rate Control

00 – Slowest ~ 110

01 – Mid-Range 1 ~ 95

10 – Mid-Range 2 ~B 80 ps

11 – Fastest (Default) ~ 60 ps

Values are typical

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