TDP158 datasheet(27/55 Pages) TI1

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TDP158

TMDS DRIVER

TMDS RECEIVER

Zo=RT

AVCC

VCC

TDP158

www.ti.com

SLLSEX2 – DECEMBER 2016

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8.3.9 TMDS Outputs

A 1% precision resistor, 6 kΩ, connected from VSADJ pin to ground is recommended to allow the differential

output swing to comply with TMDS signal levels. The differential output driver provides a typical 10-mA current

sink capability, which provides a typical 500-mV voltage drop across a 50-Ω termination resistor.

Figure 24. TMDS Driver and Termination Circuit

Referring to Figure 24, if VCC (TDP158 supply) and AVCC (sink termination supply) are both powered, the TMDS

output signals are high impedance when OE = low. Both supplies being active is the normal operating condition.

A total of approximately 33-mW of power is consumed by the terminations independent of the OE logical

selection. When AVCC is powered on, normal operation (OE controls output impedance) is resumed. When the

power source of the device is off and the power source to termination is on, the IO(off), output leakage current,

specification ensures the leakage current is limited 45-μA or less. The clock and data lanes VOD can be changed

through I2C reg0Ch[7:2], VSWING_DATA and VSWING_CLK.

8.3.10 Slew Rate Control

The TDP158 has the ability to slow down the TMDS output edge rates. As the clock signal tends to be a primary

source of EMI the edge rates have been slowed down. There are two ways of changing the slew rate, Pin

strapping for clock lane and I2C for both clock and data lanes. See Table 5 and Table 6.

Table 5. TMDS_CLK Output Slew Rate Control

Pin 34

Reg0Bh[7:6]

General

Typical Value (ps)

Slowest

215

01 (Default)

Mid-range 1

185

Mid-range 2

155

Fastest

125

Table 6. TMDS_D0, D1, D2 Output Slew Rate Control

No Pin Control

Reg0Ah[1:0]

General

Typical Value (ps)

Slowest

110

Mid-range 1

Mid-range 2

00 (Default)

Fastest

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